JPS58192078A - Bit image memory processing system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention The present invention relates to a bit image memory processing method for an ORT or high-speed printer control circuit used in a computer or a word processor.

Prior Art Conventionally, documents, graphs, etc. can be displayed on fORT,
Alternatively, when outputting to a high-speed printer, the graphic control circuit writes one page's worth of output from the printer control circuit into the image memory, reads it out, and outputs it to the output device. O with such an image memory 1
When writing characters such as %A/N (alphanumeric characters) and Chinese characters to the image memory in an I'IT or a high-speed printer, there are cases where the character breaks cannot be sent in byte units.

For example, as shown in FIG.
) is 9 bits and letter 7/8 (Ll) is 8 bits, in order to display this on kORT, the first character A must send 1 bit more than the byte break (indicated by ) in memory. , the next character B must send 2 bits more than the memory break, and the next character 0 must send 3 bits more than the memory break. Conventionally, all of this has been controlled by software, but it is not practical because it takes too much time. Also, no 1-do wear! If controlled, the circuit would be extremely complicated, leading to increased costs.

OBJECT OF THE INVENTION An object of the present invention is to solve these conventional problems by providing a method that enables writing to image memory at relatively low cost and at high speed using both software and hardware. The purpose is to provide a full range of image memory processing methods.

Summary of the Invention In order to achieve all of the above objects, the bit image and
The memory processing method is OR with image memory.
Or, in a processing device such as a printer, character
The bits for each character and line extracted from the generator
It has a register that shifts the pattern data by the number of bits of the shift when outputting it with a shift from the character break, and a register that sets a mask bit by the number of bits of the shift. It is characterized in that the outputs of the master registers are ANDed and written to the image memory.

sm example of the invention FIG. 2 is a diagram showing the contents of an image memory for outputting all characters in FIG. #1.

When displaying characters A, B, O...YrORT in Figure 1, by scanning page 1't-1st line, 2nd line, and 3rd line of OR〒 in order up to the 8th line, The character W' on the first line at the top is displayed, and the next second line of characters is displayed by scanning 8 lines in the same manner. In this case, the contents of the image memory are
As shown in the figure, the bit pattern data of the first line is written to bits bc, ~b of the first row and bit b of the next row, and the bit pattern data of the second row is written to bits b0~b of the second row. 3rd line beep) bo, b.

The pattern data of the first line of 1 is written to 3.
Bit 1 of row. ~b, and bit b in the fourth line.

The pattern data of the first line of 0 is written in ~b. Then, because the body 7 ace (B F) cannot be cut at the end of the byte, there is a space (s) at the end of the character.
p) Insert dora).

FIG. 3 is a diagram showing the character pattern of the letter B.

That is, the CO Yarakuta Pattern Generator (CO
) The bit pattern shown in FIG. 3 is stored in the area of the letter B. As usual, body 7 ace (
If BIF) is 1 byte, you can read the 1st line to the 8th line sequentially and write 1 byte at a time in the position of the character B for each line in the image memory. If the number of bits is 9 bits or more, the 1st line to the 8th line read from the character generator must be written into the image memory in the arrangement shown in FIG.

FIG. 4 is a diagram illustrating the operating principle of the present invention.

FIG. 4 shows a method for writing into the second line full image memory of the character B shown in FIG. 3 in the arrangement shown in FIG. In other words, 2 on the 2nd line in Figure 2.
Spaces and other characters are written in bits b, , b, of the row, and the character B is written only in bits b, ~b.
The second line of pattern data is written.

The fourth VJ (&) is the content read from the second line byte of character B, which is shifted twice by the full shift register to form the bit array shown in Figure 4 (b).

In the present invention, when shift writing is performed kn times, fn mask bits are set. In FIG. 4(b), a 2@ shift write is performed, so two mask bits (b, 1b1) are set as shown in FIG. 4(0). Then, when writing to the image memory,
) and the contents of Figure 4 (0) [take the logical product] and write it as the PIF content of Figure 4 (+1).

The present invention uses both software and hardware to set the registers of the 4th WJ (a) and the 4th el
The setting of the mask bit in J (o) is performed by all software, the shift operation in Figure 4(b), the AND operation in Figure 4(, i), and the write operation to the image memory are performed by all hardware. Figure 15 is a pull diagram of a bit image memory processing system showing an embodiment of the present invention. 1 is a micro program, 2 is a ROM/RAM, 3 is a character generator (CG), and ' is an image memory (MG).
M), 1 bit x 11 Kbyte shift register, 5 is the shift register for character generator 3t-shift/write, 6 is the counter for shift/write (SIFT 0NT), and 6' sets counter 6. Latch, 7 is an AND gate, 8 is a bit mask register (MARKREG), Q is an AND gate between the memory chip select signal O3 and the output of bit mask register 8, and the gate outputs the entire image memory L. Chip select AND gate, 10 is DM
A (Miroot Memory Access
) is a controller.

Figure 6 explains the operation of software and software using Figure 6 and Figure 6, which are 70-charts of bit image memory processing shown in the first embodiment of the present invention.

In step 11, the digit counter (K]jTA 01iT) indicating the OG address and the shift counter (
8 FT 0NT) 6 and mask register (MMU S
K ``e)'' Initialize the image memory 4 address (MG ADR) and tl to all 0''. Next, in step 12, the number of shifts (8 FT
0NT) f latch 6', set the mask bit in mask register 8, and then set the digit counter (
[lTA 0NT) From aG address yDMA
10, the address of the image memory 4 and the value of the transfer counter are also set to DMA10, and activation is performed (steer 213).

After this, processing is done by hardware.

That is, at the beginning of each byte transfer, the number of shifts is set in the shift counter 6 from the latch 6'. Then, when the data of CG3 is read out and set in shift register b, the shift output of shift counter 6 is manually input to shift register 6 by AND gate 7 in synchronization with the clock footer (OLK). By doing this, it is shifted by the number of shifts.

Thereafter, when writing to the image memory 4, the chip select signal (O3) is not sent to the bits masked by the AND gate 9, so the contents of the memory are not changed for the bits F, and only the bits that are not masked are Written to image memory 4. All this, DMA
The circuit 10 repeats the process for the number of transferred bytes. 86
In step 14 of the figure, it is determined whether or not the DMA11 work has been completed, and if it has been completed, the image address (AMG ADR) is inverted by +8 in step 15, for example, plan 2.
The process moves on to writing in area B, which covers the third line of the lth line in the figure. In step 16, the same processing as in step 12 is performed, except that the bit to be masked is on the right side instead of on the left side. Therefore, when all mask bits are set in mask register 8, they are set as complements. In other words, the bit position in the previous row shown in FIG. 4(c) is "0"
And "1" becomes learning. In step 17, the DMA
, and executes writing to the image memory 4. If it is detected in step 18 that the DMA operation has ended, in the next step 19 it is determined whether the number of shifts will become 8 with one more shift, and if it is not yet, in step 21 the mask register 8 is is a carry t"l", shift write, and move to the next character. Also, if one more time will result in eight times, in step 20 the shift counter 6t is set to "O" and the mask register 8 is set to 'O'.
11, image address (MG ADH)
Count up by Yr+8 and move on to writing the next character.

Also, in step 22, a digit counter, (KETAON
T), that is, whether or not the OG address ends at the remaining 11N locations, is determined, and if so, the process returns to step 12 to perform preparation processing for writing the next pronged O, for example.

In this way, the software can be executed in a relatively short time since it only requires setting parameters, and the hardware can also be implemented using a relatively simple M path. - Although we have described the case where one character area of the generator is 8 bits, it can be realized in exactly the same way even if it is 16 bits or 24 bits.

Effects of the Invention As explained above, according to the present invention, since both software and hardware are used, even if the character body 7-eighth and the letter 7-eighth are different, it can be done easily and easily with a relatively low-cost circuit. can be written to image memory in a short processing time.

[Brief explanation of the drawing]

Figure 1 is an explanatory diagram when the body face of the character and letter 7/8 are different. Figure 2 is a diagram showing the contents of the image memory for outputting the characters in figure 1. Figure 3 is the character of letter B.・Diagrams showing patterns, Figure 4 is a diagram of the operating principle of the present invention, Figure 5 is a block diagram of a bit image memory processing system showing the advantages of the invention, and Figure 6 is a diagram of an embodiment of the present invention. 70-chart of bit image memory processing shown in FIG. l: Micro Buta processor (OPU), 2: ROM
/RAM, 3 + character generator (OG
), 4: Image memory, 5: Shift register, 6
: Counter for shift/write, 6': Latch for counter setting, 7, Q: AND. Gate, 8: Bit Mask Register, 1o: 1) M
A controller. Patent ■ Vertical 1 person Ricoh Co., Ltd. -

Claims (1)

[Claims] In a processing device such as an ORT or a printer equipped with an image memory, the number of bits of deviation when outputting bit pattern data for one character and one line taken from a character generator with deviation from character breaks. It has a register for shifting and a register 1 for setting mask bits by the number of bits corresponding to the above-mentioned deviation, and performs the logical product of the output of the shift register and the output of the mask register and writes it to the image memory. Features a bit image memory processing method.