JPH0426137B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a write control device for an image memory of a non-impact printer.

Prior Art and Problems A non-impact printer obtains dot pattern data of characters to be printed from a character generator (CG) and prints the characters on paper by controlling, for example, a laser beam according to the data. Characters, in this case kanji, are represented by dot patterns such as 30 x 30 dots, but there are other methods in which laser light is controlled by reading out the dot pattern of one line of character strings for each dot line (horizontal dot row). , develops the dot pattern of one page's worth of characters into one of the pair of image memories, starts printing when the development is completed, and at the same time begins to develop the next page of characters into the other image memory. There is also a method that prints continuously while using alternately. The present invention relates to the latter, and makes it possible to store character data (dot pattern data) at precisely specified positions on the image memory at high speed.

If character data is stored in the image memory one dot at a time (in character data, one bit), this is the same as normal memory writing and there is no storage problem, but if an extremely large number of dot pattern data is stored one bit at a time, If you do that, it will take a lot of time. Therefore, a method is adopted in which a plurality of bits are written at once, and the plurality of bits is, for example, 32 bits. This assumes that the word length of the memory is 32 bits, and one address signal is used to address one of the 32 bits.
This can be done by allowing the word to be accessed.

The dot line of one character is 30 bits as described above, and if 2 bits are applied between characters, the 32 bits will become the dot line length (width) of one character.
When considering one page of X-Y two-dimensional image memory, each line in the X direction (a line or row of dots in the X direction is called a line) is divided into 32-bit units, and an address is given to the first bit of each division. ,
Since 30 lines in the Y direction is one character, each 30
The address of the first bit of the above section on the top line becomes the first address of each character.

The characters for one page may be densely packed from the beginning or upper left edge of the page to the end or lower right edge of the page, but usually there are blank spaces. Especially for headings, there is usually space on the left and right, and a little or a lot of space above and below. This is done by specifying the coordinates of each character. Although the above-mentioned start address can be used as the coordinates for specifying the character position, it is only possible to specify the above-mentioned discrete address every 32 bits. If coordinates can be specified in bit units, character positions can be specified very precisely, and any desired format can be created. However, writing is done in units of 32 bits as mentioned above, which increases the speed.

OBJECTS OF THE INVENTION The present invention addresses these problems and provides a device for storing print data in an image memory, which allows high-speed writing and fine character position specification.

Structure of the Invention The present invention provides a first data register in which n bits of data are set, and an n×m register in order to write data in units of n bits to an image memory.
A second data register that receives bit character pattern data as input, m+1 shift registers in which n bits of data are each set, and an n×m bit character pattern set in the second data register. Based on the X address that indicates the data display position and the address register that receives the address as input, and the X address set in the address register, the n Find the shift amount of the first bit writing position of the character pattern data of ×m bits, and
means for shifting the bit character pattern data by the shift amount and writing it into the m+1 shift registers; and means for sequentially selecting the character pattern data written in the m+1 shift registers for each shift register and and a multiplexer for inputting data to a first data register, and each time n-bit data is input to the first data register, the n-bit data is written to the image memory. Next, this will be explained in detail with reference to examples.

Embodiment of the invention FIG. 1 is a block diagram showing an embodiment of the invention.
IMM is print image memory and CG is character generator. Also, YAR is the Y address register, XAR is the X address register, AR is the address register,
GFR is a graphics register, CC is a clock control circuit, DR is a data register, SR is a shift register, MPX is a multiplexer, and DOR is a data output register.

The code and position data of each character in one page to be printed are sequentially output character by character from a memory (not shown), and the character code is set in the address register AR to become the address to access the character generator CG, and the position data is The X address of the data A1 is set in the register XAR, and the Y address is set in YAR, which becomes the access address of the image memory IMM. Characters have different sizes, but the character pattern data stored in the CG is for 9 dots, and each character is 32 x 30 dots. register AR
When the character code character generator CG stored in is accessed, the first (top) 1 dot line of 32 bits of the character is read out and stored in the data register DR via the data bus DB, and then the register AR is incremented by the increment mechanism. +1 by
As a result, the 32-bit data of the next dot line is stored in the data register DR via the data bus DB, and this process is repeated 30 times to extract one character's worth of dot patterns from the CG.

In this example, the sizes of characters that can be printed are 9 points and 7 points.
However, the character generator CG contains the middle 9 points, and deals with 7 points and 12 points by enlarging and reducing them. This expansion and reduction is performed during the process of transferring the pattern data of each dot line from the data register DR to the shift register SR. In other words, if the shift clock of the data register DR is stopped and the shift clock of the shift register SR is added, the data is read twice, resulting in an enlarged character pattern, and conversely, the shift clock of the shift register SR is stopped and the shift clock of the data register DR is added. Since the character pattern is overwritten and bits are truncated, the character pattern is reduced. register
If you add both DR and SR shift clocks, there will be no enlargement or reduction, and it will become a simple isometric copy. Circuit CC performs such clock control. Further, it is preferable to overwrite and read twice in an inconspicuous part of the character pattern, and this inconspicuous part differs from character to character. Control data is prepared for where to overwrite/double write for each character to be written, and the control data for each dot line of the character is taken into the graphics flag register GFR and sent to the control circuit CC. Provides clock control data.

The print character position data A1 consists of the X address and Y address of the memory IMM, as shown in FIG. i.e. image memory
The IMM can be considered to be an X-Y plane with the origin at the upper left corner, and one printed character is represented by a rectangular frame A. The scale marked on the X-axis is a division of every 32 bits as described above, and the scale marked on the Y-axis is marked every 20 lines for convenience. The width of rectangular frame A is 32 bits horizontally (X) and 30 lines vertically (Y).
The starting addresses x and y of this rectangular frame, ie, the print character area, are the X address and Y address included in the position data A1. This X address is in units of bits and not in units of divisions, so the division S may be felt as shown by x in the figure. Since the Y address is in units of lines (bits in the Y direction), it is not in the middle of the division like the X address. Therefore, Y is set in register YAR.
The address remains the access address of the memory IMM. On the other hand, the remaining bits of the X address of the register XAR except for the lower 5 bits (this indicates the address of the delimiter S) are led to the memory IMM and become the access address.

The lower 5 bits of the X address indicate the address of each bit within the 32-bit section divided by the separator S. This is further divided into four blocks, each consisting of four 8-bit blocks. Therefore, the upper two bits U2 of the lower five bits (the middle one in terms of the whole) indicate the address of the block, and the lower three bits D3 indicate the address of each bit within the block. In the present invention, these 5 bits are used to move on the register to change the position of the one-dot line of the printed character on the above classification, so that the first address x of the printed character comes to the designated position as shown in Figure 2. do. Further, this movement process is performed by selecting the block described above and shifting within the block by 8 bits or less, so that the required time is kept as short as possible.

Shift register SR is used for the above-mentioned intra-block shift, and is 6 bytes, which is the 5 bytes from register DR (32 bits when expanded, i.e. 4 bytes become 5 bytes) plus 1 byte for shift space. It has a large capacity, and after receiving one dot line worth of data from the register DR, performs a shift operation using the lower three bits D3. The 6-byte data of the register SR thus shifted is applied to the multiplexer MPX and subjected to byte selection processing by the upper (or middle) 2 bits U2.

To explain this with reference to Fig. 2b, if the first address x of a printed character falls on the 7th bit of the 3rd block _B2 of a certain category Si as shown in the figure, then in this case, the DL of the 1-dot line of the character exists across the division Si and the next division Sj, and its left and right ends are blank spaces (generally, the left end contains the preceding character,
Subsequent characters will be placed on the right edge). Here 1
Assume that the dot line DL is 4 bytes, that is, the character size is 9 points, and is not subject to enlargement or reduction. These 4 bytes of data are stuffed into the shift register SR from the bottom, leaving the top 2 bytes of the register and filling the bottom 4 bytes, as shown in FIG. The lower 5 bits of the first address x of this character are its upper 2 bits U2
is 10, and the lower 3 bits D3 are 110 (both are binary numbers), and the lower 3 bits are shifted by the 8's complement number 010 in the register SR, resulting in the following state. In other words, the data is on the 6-byte shift register SR.
It is packed into 32 bits in the middle with 14 bits and the bottom two bits left open. The contents of the shift register are written to the upper 2 bits U2 by the multiplexer MPX, and the memory access circuit MAC writes the contents for the first time.
It is extracted according to the 2-bit signal W2 indicating whether it is the second or third time. In other words, in the example in Figure 2b, it falls into category Si.
10 bits are written the first time, and 22 bits falling in section Sj are written the second time. The third writing is performed when the image is enlarged. If the start address x of the print character starts from the delimiter S and the number of bytes is 4, one writing is sufficient, and therefore, the number of times the writing is required is determined by the start address and the number of bytes of one dot line. As is clear from Fig. 2b, 10 dots on the left side of the 1-dot line DL are written with 22 zeros on the left side, and 32 bits are simultaneously written into the section Si, and then 22 bits on the right side of the dot line DL are written on the right side. If 10 zeros are added and written to the section Sj, the dot line DL can be written from the start address x as specified.

To explain the processing in the multiplexer MPX in Figure 3, this MPX is a 6-byte shift register.
Extracts the specified 4 bytes from SR and stores them in the 4-byte data output register DOR. Here, the read outputs of each byte of the 6-byte shift register SR are a, b, ... f, and these outputs are added to the four groups of input terminals of MPX as shown in the figure, and the output terminal O of MPX is One of them is taken out from ₁ to _O4 and sequentially stuffed into each byte of register DOR from the bottom as shown. multiplexer mpx
As shown in the figure, there are 9 types of input sets (therefore, the bits for selecting these are 2 bits of U2 and 2 bits of W2, a total of 4 bits), are a, b, c, d,
is 0, a, b, c, is 0, 0, a, b, ...
is f,0,0,0. As in the example shown in FIG. 2, when data is stored in the upper 1 byte of register SR and the lower 5 bytes, a=0, and there is data in b to f. If the upper 2 bits U2 of the lower 5 bits of the start address are 10, the input set is selected for the first time in MPX, and the register DOR is 0,
Four bytes a, b, and c are written. This 0 and a
The two bytes of are all 0, and the upper 6 bits of byte b are unconditionally 0. The second time, the input set of MPX is taken out, and the register DOR contains d,
e, f bytes are written. The lower two bits of this f byte are unconditionally 0.

The register DOR becomes the write data register of the memory IMM, and before writing, the 4 bytes are read and the read output is sent to the register.
It is logically ORed with the data in DOR, and the logical sum output is reset in the register, and this becomes the write data for section Si. Classification Si as mentioned above
The part to the left of the first address
It will definitely be written to Si. This time, the latter half of the character can be simply written, but in order to perform the same operation, it is also read out, the output data is ORed with the data stored in the register DOR, and it is reset to the register DOR.
Write to section Sj according to the contents of DOR. Since the read data in this case is all 0, there is no particular problem with the logic.

Effects of the Invention As explained above, according to the present invention, it is possible to precisely specify the position of print data in the print image memory.
The number of shifts can be reduced and storage can therefore be performed at high speed, which is extremely effective.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are operation explanatory diagrams. In the drawing, IMM is print image memory, CG is character generator, DR is data register, XAR is X address register, YAR is Y address register, D3
is the lower bit, U2 is the middle bit, W2 is the data indicating how many times it is written, SR is the shift register,
MPX is a multiplexer.

Claims (1)

[Claims] 1. In order to write data in units of n bits to the image memory, a first data register to which n bits of data is set, and a first data register to which n×m bits of character pattern data is input. 2 data registers, each set with n bits of data, m+1
and n× shift registers set in the second data register.
An address register that inputs an X address indicating the display position of m-bit character pattern data and an address, and writing in n-bit units set to the image memory based on the X address set in the address register. Means for determining the shift amount of the first bit writing position of the n×m bit character pattern data from the delimiting position, and shifting the n×m bit character pattern data by the shift amount and writing it into the m+1 shift registers. and a multiplexer that sequentially selects the character pattern data written in the m+1 shift registers for each shift register and inputs it to the first data register, An image memory write control device characterized in that each time a unit of data is input, n-bit data is written into the image memory.