JPS58186670U

JPS58186670U - fax receiver

Info

Publication number: JPS58186670U
Application number: JP8501182U
Authority: JP
Inventors: 松浦　竹典
Original assignee: 三洋電機株式会社
Priority date: 1982-06-07
Filing date: 1982-06-07
Publication date: 1983-12-12

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

図面は本考案ファクシミリ受信機の要部概略構成を示す
ブロック図である。１・・・モデム回路、２・・・復号回路、３・・・ライ
ンメモリ回路、４・・・制御信号検出回路、５・・・誤
り検出回路、６・・・制御回路、７・・・パターンジュ
ネレータ、８・・・ディスプレイ装置、１３・・・バッ
ファメモリ回路、１４・・・記録器。The drawing is a block diagram showing a schematic configuration of the main parts of the facsimile receiver of the present invention. DESCRIPTION OF SYMBOLS 1...Modem circuit, 2...Decoding circuit, 3...Line memory circuit, 4...Control signal detection circuit, 5...Error detection circuit, 6...Control circuit, 7... Pattern generator, 8... Display device, 13... Buffer memory circuit, 14... Recorder.

Claims

[Scope of utility model registration request]

It has a built-in pattern generator that generates a page pattern signal representing the number of pages, and this pattern generator is accessed each time one document is received, and the pattern signal obtained thereby is recorded on each corresponding recording image. A facsimile receiver capable of continuous reception as described above includes an error detection means for detecting an error in a received image signal for each document and generating an output when the number of times of detection exceeds a set value, and this detection means. 1. A facsimile receiver comprising control means for obtaining an output of the pattern signal and applying the pattern signal to a display means, and displaying the number of error pages on the display means.