JPS5816568A - Insulating gate type field effect semiconductor device - Google Patents

Abstract

PURPOSE:To improve junction withstand voltage and simultaneously increase freedom degree on design, by providing a channel stopper at an adjacent position separated from the fringe part of an active region whereon a high voltage is impressed. CONSTITUTION:The junction JD of the fringe of a drain region 2 is covered with a poly Si film 4 of the second layer, and the junction J is kept off from a P type channel stopper 6 under a field SiO2 film 5 at a fixed interval l. The stopper 6 surrounds the periphery of the region 2 from three directions but not directly contacted with the drain region. Therefore, since the region 2 whereon a high voltage is impressed is just joined to a substrate 7 with low density by the interval l, the junction withstand voltage when impressing a high voltage increases more greatly than in junction to the stopper 6 with higher density than the substrate 7. Accordingly, the ratio of width and length of the channel can be easily and freely determined based on a gate electrode 3 in a linear shape resulting also in large reduction of the occupation area of the element itself.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated gate field effect semiconductor device,
MXBIHT (M6ta) used for high voltage circuits is installed on the 1st floor.
1xnsu1ator semiaonauator
Field effect Transistor).

For example, E P ROM (erallable and
electri-cally reprogram
In bootstrap circuits, inverters, etc. in Mable ROM (mable ROM), the ring gate is surrounded by a rectangular gate electrode above the drain region in order to improve the withstand voltage.
I8] FIIT may be used. This IPI
According to CT, a source region exists in a ring shape at the periphery of the drain region with the gate electrode in between, and since the drain region does not form a junction with the channel stopper, there is a high When a voltage is applied, the drain region is less likely to be destroyed, and its junction breakdown voltage is improved.

However, as a result of the study conducted by the present inventor, in this ring gate structure, since the gate electrode is ring-shaped, the area occupied by the element is large, which is disadvantageous for improving the degree of integration (LJ), and the channel width W and channel Nagamoto ratio (W
It has been found that there are problems such as the fact that /L) cannot be freely determined in terms of layout (particularly at the corners of the gate electrode).

Therefore, an object of the present invention is to improve the junction breakdown voltage and at the same time increase the design freedom.

In order to achieve this object, according to the present invention, a channel stopper is provided at a position close to and away from the periphery of the active region where high voltage is applied in the normal structure νT, without having to do with the ring gate structure. I am trying to set it up.

゛ Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is an isometric representation of a Pootstrap circuit. In this circuit, when vPP=251F is applied as a writing voltage to the drain of the final stage M-processor SIPmTQ, in order to make the source side voltage vPPIkV, = vPP, its gate voltage V 0"f V G',
It is necessary to set it to V p-P+ 5'V, and therefore, a high voltage of V, 30 V or more, is applied to the gate. Therefore, other M devices connected to the gate of IFITQt
A similar high voltage is also applied to the drain region or source region of icTQm, Qi, and there is a risk that this voltage will exceed the junction breakdown voltage and lead to junction breakdown.

In order to prevent this, the present embodiment is constructed as shown in FIGS. 2 to 4, where bonding failure is a problem.

In other words, Reiko 81F1! 'r(2) The N+ type source region 1 and drain region 2 themselves are formed facing each other with the polysilicon gate electrode 3f in between, as in a normal structure, but it should be noted that the drain region 2 Peripheral joint J
D is covered with a second layer of polysilicon film 4, and junction J is separated from P-type channel stopper 6 under fields sio and ds by a predetermined distance t. Of course, although the channel stopper 6Fi surrounds the drain region 2 from the t3 direction, it is extremely important that it is not in direct contact with the drain region (no PM junction is formed) as in a normal structure.

Accordingly, the drain region 2 to which a high voltage (for example, 30 V or more) is applied is connected to the semiconductor substrate 7 with a lower concentration due to the above-mentioned interval t.
Since only a junction tube is formed with the channel stopper 6 with a higher concentration than the substrate 7, the junction withstand voltage when a high voltage is applied increases significantly (for example, several tens of V or more) As a result, sufficient junction breakdown voltage is exhibited.In addition, the polysilicon film 4 plays an important role in determining F4t* during the above process, as will be described later, and also requires changing the usual manufacturing process. The source region II/c is in direct contact with the P-type channel stopper 6 because no high voltage is applied to the source region II/c. It's fine.

Although it has a simple structure in which the source and drain regions are all formed on both sides of the straight gate electrode 3t, it is possible to achieve a high breakdown voltage.
The ratio of the channel width W to the channel length L (W/L) can be easily and freely determined based on the linear gate electrode 3, and the area occupied by the device itself is also significantly reduced. It will be possible. Therefore, the layout (design) of the nine elements is easy and the degree of freedom is increased.

In addition, in Figures 2 to 4, 8#'i is the gate acid and dielectric film, and 9 is the first layer polysilicon film (gate electrode).
30 is an 8103 film on the surface, 10 is 810 mJI on the surface of the second layer polysilicon film 4, 11 is a phosphorus silicate glass film, 12 is a source region, and 13 is a drain region.

Next, a method of manufacturing the above-mentioned M-work 81FICT will be explained with reference to FIG.

First, as shown in FIG.
Technology for element isolation, )”8101
[5, -FIL channel stopper 6, gate oxide film 8t
- formation and further chemical vapor deposition techniques (a V :O,)
After phosphorus treatment on the polysilicon film grown on the entire surface,
Patterning is performed using known photoetching. As a result, the 18FROM memory cell has a polysilicon film 1.
4 is left as is, and on the other hand, MI8F of the peripheral circuit M8F] CT game) ml pole 15° bootstrap circuit.
Gate voltage of Kτ.

3t poles are formed respectively.

Next, as shown in FIG. 5B, each polysilicon film 3.14.
After the surfaces of 15 are thermally oxidized to form 810 m squares 9, a second layer polysilicon film 4 is grown over the entire surface by CVD.

Next, as shown in FIG. 5C, a photoresist 16 is applied to the entire surface, and only the memory cell is etched into a predetermined pattern by known exposure and development processing, and other peripheral circuits sFi are etched.
Cover the dead. In this state, the photoresist 16f
: As a mask, polysilicon film 4, 810 layers 9, polysilicon film 14, 810 layers are sequentially etched.

Then, as shown in FIG. 5D, another photoresist 1 is applied over the entire surface.
7 and patterned it using known exposure and development processes to cover the memory cells but leave the rest in a predetermined pattern. Then, using this photoresist 17 as a mask, 2
Layer polysilicon film 4 and base layer 810*M8.9'
By sequentially etching the polysilicon film 4, an offset gate structure is formed in the peripheral circuit area, and a polysilicon film 4 is left over the element region and field 8101 film in the high voltage circuit.

Then, as shown in FIG. 51H, after removing the photoresist 17, phosphorus or arsenic is introduced into the substrate 7 by vapor phase diffusion or ion implantation to form the M+ type active region 12 as the source or drain region of each IIT. .18,19
．． 20, 21, and 22 are formed with self-aligned lines, respectively.

At this time, on the high voltage circuit side, since a part of the polysilicon film 4 is located on the surface of the substrate 7, impurities are not introduced under that part, and the H-type region +2 is a field. SiO3 film 5 (i.e. channel stopper 6
) will be formed at a distance from the formation field.

Next, as shown in Figure #5F, a B101 film 1 (a B101 film 1 is grown on the surface of each polysilicon film 40 by thermal oxidation treatment (1, 81 membrane 9 on the surface of the first layer polysilicon film 3, 14, 15), respectively. A glass film 11 of phosphorus silica is deposited on the entire surface by , cvn.

Next, as shown in FIG. 5G, the glass film 11 and the base layer B1 are coated.
The 01 film was sequentially etched using known photoetching,
After forming each contact hole, aluminum is deposited on the entire surface using a known vacuum evaporation technique, and this is patterned by photo etching to form each aluminum electrode or wiring 12.
．． 13.23° and 24.25°, respectively.

In this way, in the memory cell, polysilicon group 14t
- Floating gate and polysilicon l[4&
- The M-8PET used as a control gate is surrounded by a high-voltage M-8FK block with an offset gate structure, and the high-voltage M-81FR'l shown in Figure 3 is located in the high-voltage circuit section.
' are created respectively.

As can be understood from the above manufacturing process, the junction J on the drain side in the FIT from M in the high voltage circuit according to this embodiment
The overlying polysilicon film 4 (see FIGS. 2 and 3) is formed in common with other circuit parts in the steps shown in FIGS. 5B to 5D, and the second layer polysilicon film is etched at the same time. This is obtained by Therefore, it is only necessary to partially change the mask pattern for etching the second layer polysilicon film in the normal manufacturing process. Moreover, the fifth
The impurity introduction work shown in Figure B can be done at the same time as other circuit parts.
The second layer of polysilicon film is also used as a mask at this time. In this way, the structure according to this example is
It is very convenient because it can be created without substantially changing the normal control process.

Although the present invention 8A has been illustrated above, the above-mentioned embodiment can be further modified based on the technical idea of the present invention.

For example, the polysilicon film 4 above the junction J described above is also extended over the junction J' at the periphery of the source region l as shown by the dashed line in FIG. 2 (that is, the polysilicon film 4 is formed in a ring shape) ). In addition, the conductivity type of each of the above-mentioned conductor regions is converted to the reverse type, and the P channel M
It may be tT, or 0M0B (Oomplelen
It may also be a tory MOS type device. Note that the present invention is applicable not only to the above-mentioned device example but also to various circuits in which a high voltage is applied to the active region and which requires a high withstand voltage.

[Brief explanation of drawings]

The drawings show an embodiment of the present invention, and FIG. 1 is an equivalent circuit diagram of a bootstrap circuit, and FIG. 2 is a high-voltage M-engine 81! The plan view of ET, Figure 3 is x-xsIyr of Figure 2.
The top view, Figure 4 asz Figure 0Y-Y line sectional view, Figures 5A to 5G are
3A and 3B are cross-sectional views illustrating, in order of steps, a method for producing the main parts of a ROM. 1 is a source region, 2 is a drain region, 3 is a silicon gate electrode, 4 is a borin 1) contact M1. (2nd layer),
6 P-type channel struts/(, JDI/'iPM junctions. Figure 1, Figure 3, Figure 5A, Figure 5', C).

Claims (1)

[Claims] 1. A gate electrode is provided between a pair of active regions functioning as a source or drain region, a lateral position K close to the peripheral edge of the active region to which a high voltage is applied among the pair of active regions, and the peripheral edge. An insulated gate field effect semiconductor device characterized in that a channel stopper is provided at a predetermined interval from tW.