JPS6015944A - Semiconductor device - Google Patents

Abstract

PURPOSE:To flatten a semiconductor device through an easy process, and to reduce wiring capacitance by reticulately forming a narrow insular region in an isolation region. CONSTITUTION:A collector buried layer 2 is formed on the surface of a Si substrate 1, a Si epitaxial layer 3 as an active section for a transistor is shaped on the layer 2, and the whole is thermally oxidized. Grooves 5 approximately vertical to Si are formed, and ions are implanted while using residual SiO2 films 4 as masks. The SiO2 films 4 are removed, a thin SiO2 film 7 is formed on the surfaces of the grooves through second thermal oxidation, and a SiO2 film 8 in thickness in the same extent as the depth of the grooves is deposited on the film 7. The SiO2 film 8 is etched to obtain a flat surface. The width b of the groove must be brought within approximately one and a half times as long as the depth of the groove. It is preferable that the width (a) of Si of island sections is brought to the size of one fifth or less of (b) in order to reduce wiring capacitance. Openings are bored to a passivation film 18, and a base electrode 19, an emitter electrode 30 and a collector electrode 21 are formed, thus completing the transistor.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a semiconductor device, and more particularly, a method for electrically isolating a plurality of semiconductor elements from each other by filling a groove formed in a semiconductor substrate with an insulator. - related to a semiconductor device.

[Background of the invention]

The method of forming a trench in a semiconductor substrate and filling the trench with an insulator to isolate semiconductor elements requires a much smaller area and parasitic capacitance than the conventional selective oxidation method. This method is suitable for highly integrated and high-speed LSIs. However, since it is necessary to fill in the insulator flatly into grooves of various groove widths required for LSI, there is a drawback that the process for flattening becomes complicated. Therefore, a method has been used to make planarization easier by limiting the width of the groove, but limiting the width of the groove generates unnecessary active area sol, increases wiring capacitance, and reduces the operating speed of the circuit. There were drawbacks.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device which can eliminate the drawbacks of the prior art described above, which can be planarized through a simple process, and which can reduce wiring capacitance.

[Summary of the invention]

In order to achieve the above object, the present invention provides a mesh of narrow island-like regions in the isolation region to facilitate flattening and at the same time increase the ratio of the groove width to the width of the mesh island to 5. By more than doubling the amount, the wiring capacitance is effectively reduced. Since the island-like regions are not linear but mesh-like, when a narrow island-like region is provided, the linear shape is weak against lateral forces,
The islands were prone to breakage and damage during cleaning and other processes, but this drawback has been eliminated.

[Embodiments of the invention]

The invention will now be described in detail using embodiments relating to the fabrication of bipolar integrated circuits.

As shown in FIG. 1, a collector buried layer 2 is provided on the surface of a Si substrate 1, and an S
After forming the i epitaxial layer 3 (thickness 1 to 1.5 μm), thermal oxidation is performed to form the 5i02 film 4, and the above-mentioned 8 L O2 in the region where the groove is to be formed is further etched using a photoetching method. The membrane was selectively removed.

Next, as shown in FIG. 2, a substantially perpendicular groove 5 is formed in the Si using a well-known dry etching technique such as reactive sputter etching, and ion implantation is performed using the remaining 8102 film 4 as a mask to form the groove. A diffusion layer 6 to prevent a channel was formed on the 3i substrate at the bottom of the S i 021!, as shown in FIG. , @4 is removed and thermal oxidation is performed again to form a thin 8iC)+ on the surface of the groove.
A film 7 (thickness: 50 to 200 nm) was formed, and an 8j02 film 8 having a thickness comparable to the depth of the groove was deposited thereon by the usual CVD method.

Next, as shown in FIG.
A flat surface was obtained by etching.

Here, the wide island 9 is a region where elements such as transistors are formed, and the narrow island 10 is a waste region to facilitate planarization.

Here, the width of the groove needs to be within about 1.5 times the depth of the groove (a condition under which no concave portion of the 8102 film 8 is formed in the center of the groove). However, it is preferable that the SiO width a at the high part is 115 or less than b in order to reduce the wiring capacitance. Therefore, it is necessary to make the width a as small as possible, but when this width becomes about 0.5 μm, the strength becomes weak and a long pattern becomes easy to break. Therefore, the narrow islands 10 can be prevented from being damaged by arranging the narrow island pattern 11 in a mesh pattern as shown in the plan view of FIG. Here, the mesh repeating interval does not necessarily have to be equal in the X direction and the Y direction; if one direction is set to the interval necessary for flattening, the other may be set larger. Further, since isolation is required around the region 12 where the element is formed, it is necessary to provide a gap 13 between the region 12 and the mesh pattern as shown in FIG. Furthermore, if a long, unsupported turn occurs due to the provision of a gap, it is desirable to add an island as shown by the broken line 14.

Now, as shown in FIG. 6, after FIG. 4, a diffusion layer 15 for taking out the collector, a base diffusion layer 16, and an emitter diffusion layer 17 are formed.
8, a base electrode 19, an emitter electrode 20.
A collector electrode 21 was formed to complete the transistor.

In this example, the case of vertical groove shape is described.
It is also possible to slope the top of the groove, as shown in FIG. In this case, the width of the active region becomes slightly smaller, but the buried 5JOz film has advantages such as improved range and further reduced wiring capacitance. In this case, the wiring capacitance is reduced to about 1710 for the narrow case only, and the circuit speed is improved by about 50 degrees.

〔Effect of the invention〕

In the Ebora LSI fabricated in this way, the thick 5in2 film 8 exists in the isolation region, and the width of the island 10 in the isolation region is small, so the wiring capacitance i is reduced to about 115 compared to the case of only a narrow trench. The circuit speed has been increased by about 30 chips.

[Brief explanation of the drawing]

1 to 4 and 6 are schematic process diagrams of a semiconductor device as an embodiment of the present invention, FIG. 5 is a plan view showing the same embodiment, and FIGS. 7 and 8 are respectively in accordance with the present invention. FIG. 3 is a sectional view showing another embodiment of the invention. 1... Si substrate, 2... Collector buried layer, 3...
S1 pitaki 7 layers, 4,7.8...5iOz film. Figure 1 Figure 4 Figure 2 Figure 3 Figure 4 Figure 5 Figure 1←

Claims (1)

[Claims] In a semiconductor device in which a groove formed in a semiconductor substrate is filled with an insulating material to perform insulation isolation between elements, island-shaped islands having a width of approximately 1 μm or less are spaced within the isolation region at intervals of a certain length or less. A semiconductor device characterized by having regions in a mesh shape.