JPS5815987B2 - Frame synchronization method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frame synchronization method for transmitting data in units of frames.

In conventional block synchronization in data transmission, for example, as shown in Figure 1, the first byte of each block is an STX code, and the last byte is an ETX code, indicating the division of one block into seven blocks. be.

STX code of the first byte and E of the last byte like this
In the text between the TX code, STX code, ET
If it is safe to transfer a transmission control code such as an X code, a DLE code is inserted to enable identification of data and transmission control code.

Frame synchronization, as shown in FIG. 2, involves inserting, for example, an 8-bit flag word F into each frame.

If data with the same bit pattern as flag word F is transferred, to avoid misidentifying it as flag word F,
The data was transmitted by inserting "0" as shown by the arrow.

In the conventional method described above, block synchronization and frame synchronization can be established immediately by detecting the STX code or flag word F, but if a bit error occurs, one block Alternatively, one frame of data will be lost.

Also, even if it is a block transfer with a fixed number of bytes or a frame transfer with a fixed number of bits, a DLE code or 0'' bit must be inserted to ensure transparency.
Block transfer station configuring has the disadvantage that the frame transfer cycle varies.

Furthermore, in digital multiplexing (low Is transmission), it is desirable that the transmission capacity of each signal channel be constant, and when a waveform is digitized and transmitted, it is desired that sampling is isochronous.

When a frame with a fixed word length is constructed from each sample value, it is desirable that the transmission synchronization of the frame is also constant.

. However, as mentioned above, <DEL code or +1 Q
In the conventional synchronization method that inserts 11 bits, the above requirements are not met.

Transmission errors in sample values can be detected by interpolation using sample values that were correctly received before and after the sample value, or by transmission error detection in a system that has good transmission quality and allows for a small amount of transmission errors. If retransmission is not performed, one block or one frame may be lost as described above due to a transmission error occurring in the STX code or flag word F representing a block or frame boundary.

As a result, the impact will be significant.

The present invention protects against transmission errors in flag words indicating frame boundaries in a system in which frames are configured and transmitted using a fixed word length, ■ prevents frame data from being lost, and is economical. The purpose of this is to achieve frame synchronization in the configuration, and will be implemented and explained in detail below.

FIG. 3 is an explanatory diagram of the frame structure of the embodiment of the present invention, in which one frame is composed of N words, a flag word F is added to the beginning of the frame, and N-1° words W1 to WN
-1 data is transmitted.

FIG. 4 is a block diagram of implementation i+lJ of the present invention,
PS is the main unit consisting of the processor CPU and memory ML Hiro1, etc., H section, CB is the common bus, TC is the transmission control section, LIF
is a line interface section consisting of a demodulator DEM, etc., and SR
G is a shift register for serial/parallel conversion, DRG is a data register, FD is a flag detection circuit, FRG is a flag verification register, CNT is a counter, REG is a flag search command register, 01 to G3 are inhibit gates, and G4 is an AND gate. be.

The received data RD demodulated by the demodulator DEM of the line interface section LIF is serially transferred to the shift register SRG and set in the shift register SRG in accordance with the pit clock RT.

This bit clock RT is applied to a counter CNT via an inhibit gate G1, and a timing signal is output every time the number of bits of a word is counted.

This timing signal is applied to data register DRG and flag verification register FRG via inhibit gate G2, and data register DRG reads and sets one word of data from shift register SRG in parallel according to the timing signal.

Further, the flag detection circuit FD determines whether or not one word of data set in the shift register SRG is a flag word F. If the data is a flag word, the flag detection circuit FD selects a flag verification register FRG, an inhibit gate G3, and an AND gate G.
Add signal to 4.

Therefore, the flag word will be detected and set in the flag verification register FRG by the timing signal.

Furthermore, the timing signal via the inhibit gate G2 becomes an interrupt signal for the texture section PS, and the processing section PS transmits the contents of the data register DRG and flag verification register FRG via the gutter bus CB. After reading, the contents of the flag verification register FRG are checked every N words to confirm the synchronization state.

When the flag word is not detected in the texture of the read data in this processing unit PS, the texture is executed as an accidental transmission error, and when the flag word is not detected M times in a row, Out of sync.

FIG. 5 is an explanatory diagram of the operation. As shown in a of the figure, one frame is composed of N words, and N-1 words W0 to WN
When the flag word F is inserted every -1, the counter CNT generates a carry by counting the number of bits of one word of the pit clock, and uses this as a timing signal as described above.

That is, as shown in FIG. 5, the signal is generated at every word interval and serves as an interrupt signal to the processing unit PS.

Since the flag verification register FRG is set by the timing signal when the flag word F is detected, the fifth
It will be as shown in Figure C.

That is, if the flag verification register FRG is set every N words, it is determined that frame synchronization has been established.

Sync! In the 7-yen error state, a timing signal is generated as shown in FIG. 5d, and the flag word is detected using the second half of the word and the first half of the next word as one word. Detecting the flag word consecutively more than M times, such as in a synchronous state, cannot occur except by pure chance.

In the processing unit PS, the flag verification register FRG is not set for each frame period consecutively M times or more.

When it is determined that this is the case, the flag search command register REG is set.

The set output signal becomes the inhibit input of the inhibit gate G2, and also serves as the input of the AND gate G4 and the inhibit gate G3.

Therefore, each timing signal is inhibited.
3 becomes '1'', the inhibit gate Gl is closed, and the pit clock to the counter CNT is inhibited.

This operation continues until the flag word is detected by the flag detection circuit FD.

When a flag word is detected, the flag search command register REG is reset at the timing of the output signal of the counter CNT.

FIG. 5e shows the set output of the flag search command register REG. If a flag word is not detected consecutively M times or more, the shift flag search command register REG is set from the processing unit PS, and the timing is as described above. Each time a signal is output from the counter CNT, the inhibit gate G1 is closed to inhibit pit clock counting, the period of the timing signal is delayed, and a flag word is detected.

When this happens, the inhibit gate G1 becomes open, so the timing signal in that case becomes as shown in FIG. 5f.

Then, by detecting the flag word, the flag verification register F
RG is set as shown in FIG. 5g.

Continuous in textured part PS. It is determined that synchronization is established when the flag word is detected for the number of times, and if the flag word is not detected for the number of times or less, resynchronization is performed by setting the flag search command register REG again. Have them do the action.

As described above, forward protection and backward protection of frame synchronization are controlled by the program of the processor CPU of the processing unit PS.

As explained above, the present invention uses a frame structure with a fixed word length, inserts and transmits a flag word of M bits (M is an integer of 2 or more) indicating the boundary between frames, and transmits a flag word on the receiving side. In the method of detecting words and achieving frame synchronization, a serial/parallel converter circuit such as a shift resistor SRG that reads the received signal in synchronization with a clock and converts it into a parallel signal, a flag detection circuit FD, and an M Counter CN that outputs a carry signal for each bit
T, a flag verification register FRG that sets a flag detection circuit FD with a carry signal, and a processing unit PS that reads the output of the flag verification register FRG with a carry signal, and has a processing unit PS that reads the output of the flag verification register FRG with a carry signal, and a flag word is not detected consecutively for a predetermined number of times or more. When the processing unit PS determines that the synchronization is out of synchronization, it prohibits the manual input of the clock to the counter CNT, and when the flag word is detected, it restarts inputting the clock to the counter CNT and sets the flag word to a predetermined value. If it is detected consecutively for a number of times or more, the processing unit PS determines that synchronization has been established, and therefore protection is provided against flag word transmission errors as long as there are no consecutive errors for a predetermined number of times or more. , ■ Frame data will no longer be lost.

As data transmission using a frame structure with a fixed word length, there is a digital multiplex transmission method for the purpose of waveform analysis, for example. By applying the invention, one frame of data is not lost, and synchronization establishment and synchronization loss can be determined and controlled by an interrupt during data texture in the processing unit PS.
Frame synchronization can be achieved with a relatively simple configuration.

Also, every time one word of tarok is counted by one counter CNT, the detection output of the flag word is sent to the processing unit P.
S, the processing unit PS determines whether synchronization is lost or synchronization is established, and if it is determined that synchronization is lost, the counter CN
The flag word is detected by controlling the tarlock to T, and synchronization can be easily carried out.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the conventional block synchronization transmission format, FIG. 2 is an explanatory diagram of the conventional frame synchronization transmission format, FIG. 3 is an explanatory diagram of the transmission format of the embodiment of the present invention, and FIG. 4 is an explanatory diagram of the transmission format of the conventional frame synchronization. A block diagram of an embodiment of the present invention, FIG. 5 is an operation explanatory diagram. PS is a processing unit, CPU is a processor, MEM is a memory,
CB is a common bus, TC is a transmission control unit, DRG is a data register, SRG is a shift register, FRG is a flag verification register, FD is a flag detection circuit, CNT is a counter,
REG is a flag search command register, LIF is a line interface section, and DEM is a demodulator.

Claims (1)

[Claims] 1. In a method in which a frame is constructed with a fixed word length, a flag word of M bits (M is an integer of 2 or more) is inserted to indicate the boundary between frames, and the frame is synchronized by detecting the flag word, a serial conversion circuit that reads the received signal in synchronization with the taro clock and converts it into a parallel signal; a flag detection circuit in which the parallel signal from the serial-parallel conversion circuit is set;
a counter that counts the clock and outputs a carry signal every time M bits are counted; a flag test register that sets the flag detection circuit using the carry signal from the counter; and a process that reads the output of the flag test register using the carry signal. and when the flag word cannot be detected continuously for more than a predetermined circuit according to the output of the flag verification register, the processing unit determines that synchronization is out of order and prohibits manual input of tarot to the counter;
On the other hand, when a signal indicating flag detection is output from the flag detection circuit, the input of the rank to the counter is repeatedly performed, and the processing section determines that the flag word has been used continuously for a predetermined number of times or more. A frame synchronization method characterized in that it is determined that synchronization is established when: