JPS58151749A - Packet multiplying device - Google Patents

Abstract

PURPOSE:To decrease the quantity of hardwares, by decentralizing all procedures for transmission of data and at the same time by simplifying the access method to a common data memory. CONSTITUTION:The non-paket terminals are connected to a data memory 60 via circuits 11-1n, circuit control parts 21-2n, transmission control processors 31-3n and a memory bus 70 respectively. At the same time, a packet exchange station is connected to the memory 60 via a multiplex circuit control part 40 and a transmission control processor 30. Thus the communication is performed between the exchange station and the terminals via the memory 60. The processor 30 transmits and receives data between the memory 60 and the part 40 on the basis of the transmission control procedure corresponding to the exchange station, while the control part 40 controls the assembly and disassembly of a data packet. The processors 31-3n transmit data between the control part 21- 2n and the memory 60 with the transmission control procedure corresponding to the non-packet terminals. A memory access control part 80 controls the access sequences to the memory 60 for the processors 30-3n.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a packet multiplexing apparatus, and more particularly, to accommodating and assembling a plurality of non-packet terminals into packets.

The present invention relates to a packet multiplexing device that sends and receives decomposed data into packets to and from a packet conversion station.

A conventional packet multiplexing device of this type will be explained with reference to FIG. FIG. 1 is a block diagram showing an example of the configuration of a conventional packet multiplexing device.

In the figure, multiple non-packet terminals with different synchronization methods (e.g., start-stop type, synchronous type, etc.) and transmission control procedures (e.g., basic data transmission control procedure, high-level data link control procedure, etc.) are generally accommodated in each terminal. Line 11. The terminal accommodation line control units (hereinafter simply referred to as line control units) 21° to 2nK are connected via the line control units 21. ~2n is sent to the line control channel 90 via the line control unit y)3r. Further, the nine multiplex route recall control unit 41 which is connected to the packet switching center via the packet multiplex route 50 is connected to the line control channel 91 .

Further, the line control channels 90.91 are connected to a main memory circuit 93 and a central control circuit 9 via a processor bus 92.
Connected to 4. The main memory circuit 93 stores programs such as data transfer procedures and data to be transferred, and the central control circuit 94 executes the programs, that is, processes all procedures at once. .about.2n are terminal accommodation lines 11. to 2n corresponding to the synchronization method of non-packet terminals, respectively. Low-speed transmission/reception data to/from ~1n (e.g. 2
00 bits/second data) is disassembled and assembled into character units. @The line control unit 3 has a buffering function for temporarily holding line-side transmitted and received data on a so-called professional basis, and the line control channel 90 is connected to the central control circuit 94.
The multi-way line control unit 41 reads/writes data from/to the main memory circuit 93 and transfers data to/from the line control unit 3 according to instructions from the main memory circuit 93 . High-speed sending/receiving data (e.g. 2400
decomposes (bits/second packet multiplexed data) into character units/
The packet multiplexing strategy 500 has a buffering function in block units for one line. The line control channel 91 transfers data between the main memory circuit 93 and the multipath line control section 41 according to instructions from the central control circuit 94. Next, the operation of this example will be explained.For example, low-speed data from a non-packet terminal via the terminal accommodation line 1it is assembled character by character by the line control ff121 and buffered in the line control ff12 and ff3. Low-speed data from other non-packet terminals is similarly buffered in the line control unit 3. The line control unit) 3t! These low-speed data are reversely routed through the control channel 90 according to instructions from the central control circuit 94. The main memory circuit 93
The data is stored in a predetermined data area. Subsequently, the line control channel 91 outputs the price axis data according to instructions from the central control circuit 94 and transfers it to the multipath line control section 41.

The multipath line control section 41 decomposes these read data into character units and sends them in a predetermined format and at speed f (high speed) to the packet switching center via the packet multiplex path 50tl.

The operation when high-speed data from the packet switching center is transferred to a desired non-packet terminal in a format and speed (low speed) prescribed by the terminal is also similar to the above, so a description thereof will be omitted. Note that the components (including the line control channel) other than the line control unit in this example are usually installed in duplicate as a redundant configuration.

Therefore, in the packet multiplexing device of this example, the processing capacity of the central control circuit must be increased, the main memory circuit must also be increased in size, and a line control channel must be installed, which has the drawback of increasing hardware and making it expensive. Ta.

SUMMARY OF THE INVENTION An object of the present invention is to provide a packet multiplexing device which solves the above-mentioned drawbacks by distributing the processing of all data transmission procedures and simplifying the method of accessing a common data memory.

The packet multiplexing device according to the present invention includes a terminal accommodation line control unit that assembles and disassembles transmitted and received data in character units in accordance with the synchronization method of the non-packet terminals for each non-packet terminal accommodation line, and a transmission control block that executes transmission control procedures, a multipath line control unit that assembles and decomposes data sent and received with the bucket multipath into character units, and executes data transmission and reception with the packet multipath. a multi-path transmission control processor, a data memory section for temporarily storing all of the transmitted and received data, a memory bus connected between the data memory section and all of the above-mentioned processors, and the data memory. Access to the department? The present invention is characterized in that it includes a memory bus access control unit IT that is periodically allocated to all the processors. The memory bus access control section includes a counter that detects black and red signals, and an I! If the clock signal is delayed by a predetermined time and outputted, the clock signal is delayed by a delay element, and a decoder is configured to decode the input from the counter and the delay element. # sign.

Next, the present invention will be explained using FIGS. 2 and 3.

FIG. 2 is a block diagram showing the configuration of an embodiment of the packet multiplexing device of the present invention. In the same figure, a plurality of non-packet terminals, a packet accommodation line 11. ~ lnsln side control section 21
．． ~2n, packet, to multipath 50 and package y) 3e!
1! L) i61d has the same configuration and functions as those in the conventional packet multiplexing device, and is denoted by the same reference numerals as in FIG. The multipath line control unit 40 disassembles and assembles the data transmitted and received with the packet multipath 50 into character units. The line control unit 21. . . . . . . . . . . . . . . . . . . . . . . . ~
3n and the multipath transmission control processor 30, and these bromo, 31. ~3n, 30 are each connected to the data memory 60 via a memory path 70.

Further, the multipath transmission control block 30 is a signal a10.
0 and 110), said transmission control processor 31.
~3n is the signal line 101. .about.10n are connected to the memory bus access control section 80, respectively.

The data memory 6o temporarily stores data transmitted and received between the non-packet terminal and the packet switching center, and the multipath transmission control processor 30 stores high-speed data between the multipath line controller 40 and the data memory 60. The multipath line control unit 40 executes the next process according to the next transmission control procedure according to the transmission/reception and packet switching center, and the multipath line control unit 40 uses a packet multiplexing strategy 50.
31. The transmission control program disassembles/assembles data sent/received to/from (the high-speed packet-multiplexed data) character by character. ~3n are each line control unit 21
．． 2n and the data memory 60 according to each non-packet terminal.

The memory bus access control unit 80 controls each of the processors 30, 31 . -3n access sides to the data memory 60 are periodically allocated to each of the above-mentioned blocks.

30, 31. ~3n writes to memory only within each allocated time, and multiple data memory 6
Allow access to 0.

Next, the operation of this embodiment will be explained. First, the multi-source route transmission control block 30 transmits the signal [110 to
A signal ST (with a repetition period equal to the bit width of data transmission/reception from the multipath transmission control processor 30) is applied to the memory bus access control section 80. The memory bus access control unit 80 generates non-overlapping signals ENO, ENl, -ENni- from the black signal ST and outputs these signals EN.

EN1 to ENnt-signals m100.101. ~
Periodically, the access to the data memory 60 is given to each of the processors 30, 31. to 3n by providing multi-direction transmission via the 10nt to the control processors 31. to 3n. Assign.The line control units 21. to 2n each have an end uncollected trough.
Al1. The transmission control processor 31 assembles the non-packet data from the non-packet terminal via 1n into character units.
．． ~Send to 3n. These transmission control processors 31. ~3
n performs processing according to the transmission control procedure according to each of the non-packet terminals, and sends the received data to the signals EN1 to EN1, respectively.
ENfl reception period (access to data memory 60 m
The data is stored in respective predetermined memory areas of the data memory 60 via the memory bus 70t in response to a memory write command within a certain time period. Multipath transmission control processor 30 then outputs the signal EN via signal line 100.

A memory read command is issued within the reception period, the to-be-assembled data stored in the data memory 60 is read out, processed according to the transmission control procedure according to the packet switching center, and is multiplexed as packet-multiplexed high-speed data. The data is transferred to the circuit control unit 40. The multipath line control unit 40 decomposes the high-speed data into character units and sends them to the packet multiplexing path 5.
0t- to the packet switching center. Further, the multipath line control section 40 receives all high-speed data from the packet switching center via the packet multipath 50t, assembles the data in units of characters, and transfers it to the multipath transmission control processor 30. The multi-way transmission control module 30 performs processing according to the transmission control procedure according to the packet switching center, and writes the received data to a predetermined memory area of the data memory 60 by a memory write command within the reception period of the signal ENO. The data is stored via the memory bus 70. Next, transmission control processor 3
1° to 3n issue a memory read command within the reception period of the signals ENl and ENn, respectively, and the data memory 60-
The data to be stored is read out from the memory area of , and all processing is performed according to the transmission control procedure corresponding to each non-packet terminal, and the transmission data is transferred to the line control units 21° to 2n. The line control unit 21. .about.2n decompose the transferred data into character units and transmit them to the terminal accommodation lines 11. ~Inc
h to each non-packet terminal. Note that in this embodiment, only devices that are normally used in common with all terminal accommodation lines (for example, a multipath transmission control block, a multipath circuit control unit, a data memory, a memory bus, and a memory bus access control unit) are used. ) can be installed in duplicate.

FIG. 3(al) and (bl are respectively a circuit diagram and a signal time chart showing an embodiment of the memory bus access control section in FIG. 2. In FIG. 3(a), n
- The decimal counter 801 counts the clock signal STi from the signal line 110 and outputs a value of 0. ~n-1 periodic outputs to the decoder 802. The decoder 802 outputs the output value O
1 to n-1 and sends the signal to the AND circuit 804.
The signals EN1 to ENn are periodically sent to the signal lines 101 and 101 to Ion, respectively, as signals EN1 to ENn. The delay element 803 receives the clock signal 8T.
The t-receiver is output with a predetermined time delay. The AND circuit 804 ANDs the output of the delay element 803 and the black signal 5Tt, and provides the result to the decoder 802 as the common enable signal. The AND circuit 805 outputs the inverted output signal of the delay element 803 and the black and red signals 8 through inverters 806 and 807, respectively.
AND the inverted signal of T and send the signal ENot to the signal line 100.
- Send periodically. The delay element 803. F by AND circuits 804, 805 and inverters 806, 807
) fN signals ENo, ENl, ~EN, are made so as not to overlap with each other. In FIG. 3(b),
(1) The clock signal 8T is a pulse train with a duty of 50 seconds that repeats the status of 10'' and ``1'' with a period T. (2) The output of the n-1 counter 801 is the total pulse count of the clock signal ST. is added by 1 every cycle T, and the output value is 0°1.2,3.~n-
1. o, 1. ~ will be repeated. (3) Delay element 803
The output is a pulse train of the period T, which is obtained by delaying the pulse train of the clock signal 8T by a predetermined time d. (4) Each of the signals ENQH continues for a period of time (T/2-d) from the fall of the pulse of the output of the delay element 803 to the rise of the pulse of the black signal ST, and is repeated at the period T. It is a signal train. (5) Decoder 802
Each output is between the rising edge of one pulse of the output of the delay element 803 and the falling force of the pulse of the black signal ST which is being input at the same time as the one pulse (time 1''/2-d) df
iL, signal EN1. EN2. EN3. ~E-711 is a signal train that is repeated at a period nT.

Note that the signals ENO, EN1 . The repetition period of each of ~ENn is an example. It can be set arbitrarily depending on the data transmission/reception speed with ~1n.

As is clear from the above description, according to the Kerato multiplexing device of the present invention, processing of all data transmission procedures is distributed to the transmission control processor, so the transmission control processor can be downsized, and It is possible to use LSI9, and there is no need to install an expensive line control channel.Furthermore, the allocation of access rights to the common data memory section is easy to control and the access method for each processor. This has the effect of reducing the amount of electricity and making it possible to achieve significant economicalization.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of the configuration of a conventional packet multiplexing device, and FIG. 2 is a block diagram showing the configuration of an embodiment of the multiplexing device of the present invention. Figure (al,
(bl is a circuit diagram and a signal time chart showing an example of the memory bus access control section in Figure @2, respectively. In the figure, 11, ~1n... terminal accommodation line, 21.~2n
... End-unaccommodated recovery control unit, 3... Line control unit. G, 30...Multi-path transmission control procedure, S, 3
1°~3n...Transmission control block, 40, 41.
...Multi-path line control unit, 50...Packet multiplexing strategy t60...Data memory, 70...
...Memory bus, 80...Memory bus access control unit, 90.91...Line control channel, 92...Processor bus, 93...Main memory Circuit, 94...Central control circuit, 100.10
1. ~10n, 110... Signal line, 801...
... n-1 counter, 802 ... decoder, 803 ... delay element, 804, 805 ...
...AND circuit, 806,807...Inverter. Stem l round, sugar, 2 fig.

Claims (1)

[Scope of Claims] (A terminal accommodating line control unit that assembles and disassembles transmitted and received data in units of characters in accordance with the synchronization method of the non-packet terminals for each of the 11 non-packet terminal accommodating lines; a transmission control processor that executes a transmission control procedure; a multipath line control unit that assembles and disassembles data sent and received between the packet multiplexing path in character units; and a multiplexing path that executes all data transmission and reception with the packet multiplexing path. Transmission control Bromo, Suto,
A data memory section for temporarily storing all the transmitted and received data; a memory bus connecting the data memory section and all the blocks; 1. A packet multiplexing device comprising a periodic allocation memory bus access control TflS't. (2. In the packet multiplexing device according to claim (1), the memory bus access control unit includes a counter that counts the clock signal and outputs the black signal t-receiver after a predetermined time delay. A packet multiplexing device comprising: a delay element; and a decoder that decodes inputs from the counter and the delay element.