RU2642383C2 - Method of information transmission - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: method of information transmission is characterized by the fact that information in a format of PCI-Express packets is transmitted both by serial high-speed communication links and by a parallel bus, and depending on the addresses in the packet, data is redirected either inside I-Bus controller, or to an external bus of PCI-Express and then through the RCI-Express commutator and to the other I-Bus controllers. The PCI-Express commutator is designed to transmit a packet to several I-Bus controllers simultaneously, and the I-Bus controller is designed to operate in a double speed flow processing mode. Determination of the amount of the required terminal stations and commutators with determination of the required topology of communication links between them are preliminary carried out, the used commutators and terminal devices for information reception/transmission are adjusted, the transmitted information is divided into packets for transmission by the PCI-Express standard with a payload size of not more than 4 kilobytes.

EFFECT: ensuring the use of a packet format of PCI-Express standard for transmission by both serial and parallel buses.

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Description

The invention relates to the field of computer technology, is intended for the construction of digital signal processing systems in real time.

The developed technical solution is based on the use of the bus (I-Bus), which interconnects the devices involved in receiving, relaying, processing information in real time. Via the specified bus, primary or pre-processed data is distributed for further processing. Data is transmitted in the format of PCI-Express packets.

Known system TSPANU, designed to process signals in sonar systems. Its description is given in an article by N.M. South et al. Tecnologies for Sonar Processing JOHNS HOPKINS APL Technical Digest, VOLUME 19, NUMBER 4, 1998.

Known (RU, patent 2207620, publ. 06/27/2003) digital computer complex (CVC) for processing signals in sonar systems.

The digital computer complex (CVC) for real-time processing of signals in sonar systems is a modular, reconfigurable architecture that contains a group of individual processors connected by one high-speed bus, control circuit, and shared memory. Moreover, these individual processors are based on dual-port signal microprocessors. The CVC contains several groups of individual processors, and groups of individual processors are combined into one or more modules of programmable processors (PPPs). One or several computer modules, made on the basis of universal microprocessors, and remote control modules, including one or two monitors, a remote computer, a keyboard and a manipulator, have been included in the CVCs to the inputs of the faculty modules, which are the inputs of the CVC, and radial transmission channels are included between the faculty modules of the processed signals, two Ethernet networks were introduced into the CVC, while the PPS modules are combined with one computer module, and the computer modules are combined with the remote control modules by another Ethernet network, two main bus of the Man interface type are introduced into the CVC Chester-2 for the exchange of data and control actions with external systems, with all the faculty modules connected to one, and the computer modules and remote control modules with the other main bus interface Manchester-2.

A disadvantage of the known technical solutions should recognize their unsuitability for achieving the following technical result.

TSPANU, in particular, is not optimal for real-time data processing, while it has relatively low performance, and the above-mentioned CVC does not meet the requirements of a modern data distribution complex. Namely: the CVC has ring input and output buses, which means a limited maximum bus bandwidth, and if there is a need to process a larger data stream, we run into a limitation of the complex architecture.

In I-Bus, however, they use the distribution of flows through non-blocking switches in the I-Bus controller and non-blocking PCI-Express switches, so adding an additional I-Bus controller and correspondingly increasing the input data stream does not significantly affect the performance of other devices. The I-Bus architecture and lattice in the I-Bus controller are optimized for the quantitative distribution of the incoming data stream, that is, the data is not allocated / separated by any distinctive signs inside the stream, but the data is distributed evenly across the controllers.

The technical problem solved by the developed method is to develop a new method for transmitting information between physical objects.

The technical result achieved by the implementation of the developed method consists in using the format of packets of the PCI-Express standard for transmission on both serial and parallel buses, allowing the use of existing equipment (where there are no serial transceivers), as well as simplifying the configuration of the system as a whole, which allows you to reduce power consumption.

To achieve the specified technical result, it is proposed to use the developed method for transmitting information between physical objects. According to the developed method, information in the format of PCI-Express packets is transmitted both through serial high-speed communication channels and through a parallel bus, and, depending on the address in the packet, data is redirected either inside the controller or to an external PCI-Express bus and then through the switch PCI-Express to other I-Bus controllers, while the PCI-Express switch is capable of transmitting a packet to several controllers at the same time, the I-Bus controller is capable of operating in the double processing speed mode and, moreover, preliminary determination of the number of necessary terminal stations and switches is carried out with the determination of the necessary topology of communication channels between them, using the transmission of configuration packets through the used communication channels, the used switches and terminal devices for receiving / transmitting information are configured, the transmitted information is divided into packets for transmission according to the PCI-Express standard, the size of the useful data is not more than 4 kilobytes, with each packet consisting of a header and a data field, including for recording the transmitted information, the header contains information about the type of packet, the sender address of the packet and the address of the receiver, PCI-Express levels are used as the data exchange format, namely: Physical Layer, Data Link Layer, Transaction Layer.

The developed method is based on the following provisions:

- PCI-Express packets are transmitted both through serial and parallel buses;

- Use a simplified system for configuring PCI-Express;

- Use the transmission of packets simultaneously to multiple subscribers (multicast) with a simplified configuration of this mechanism;

- The I-Bus controller has a double stream processing mode.

The I-Bus controller circuit is shown in FIG. 1. In FIG. Figure 2 shows the configuration diagram of the I-Bus controller.

The primary data comes from mezzanines (Mez1 and Mez2), then they are sent to the I-Bus controller via a parallel bus, where, depending on the address in the packet, data is redirected:

- either to an external PCI-Express bus and then through a PCI-Express switch to other I-Bus controllers;

- either to the internal data processor (Lattice) and further to the signal processors TS0 ... TS7;

- either directly to the TS0 processor.

The internal data processor of the controller, in accordance with its configuration, distributes the data among the eight signal processors TS0 ... TS7.

The bus width of the PCI-Expressy controller and switch is 2lane.

The PCI-Express switch has the ability to send a packet simultaneously to multiple controllers (multicast). A sign that a packet is addressed to several subscribers is the corresponding bit in the address. Compared to the PCI-Express standard, the I-Bus multicast is simpler, therefore, additional chip resources are not needed.

The mezzanine of the ADC transmits information in the format of PCI-Express packets to the I-Bus controller via a parallel bus. Depending on the address in the packet, the I-Bus controller forwards the packet either to the PCI-Express switch or to the packet handlers in the I-Bus controller. Communication between the I-Bus controller and the PCI-Express switch is carried out via the serial PCI-Express bus at a speed of 2.5 Gigabits / s.

In I-Bus, all data is transmitted in a packet basis of the PCI-Express standard. There are the following main types of calls (transfers and data transfer requests):

- Configuration calls. Configuration record and configuration read.

- Accesses of type MemoryWrite (data recording).

- The appeal of type MemoryRead (data reading).

In turn, calls like MemoryWrite or MemoryRead can be 32-bit or 64-bit. In the first case, packets with a heading of 3 words (3DW) are used, in the second case with a heading of 4 words (4DW).

Below are the types of packages used for exchange between the devices of the complex via I-Bus.

The format of the Configuration Package is 0 Write.

This package is used to write configuration registers of the device on the I-Bus.

RequesterID - identifier of the device that initiated the recording.

BusNumber is the bus number.

DeviceNumber - device number.

FunctionNumber - function number.

Package format Configuration Type 0 Read.

The Configuration Type 0 Read packet is used to read the device configuration registers on the I-Bus.

Completion Package Format for Configuration Read

The Completion package for Configuration Read is a response to a request to read the configuration register of the corresponding I-Bus module. The packet is sent by the I-Bus module in response to a request from the module that initiated the Configuration Read request. The Completer ID is set to the Device ID value assigned to the device. Requester ID and Tag are copied from the corresponding fields in the Configuration Read request.

The format of the package is Memory Read 3DW.

The format of the package is Memory Read 4DW.

Packets of type Memory Read are used to read information from a device on the I-Bus. The Address field of the packet contains the address of the device from which information must be read. Accordingly, Memory Read 3 DW packets use 32-bit addressing, and Memory Read 4 DW packets use 64-bit addressing.

Packages like Memory Read do not have Payload. The Length field of the first word of these packets means the Payload length that the expected Completion packet (read response) should have.

Completion package format for Memory Read.

The Completion package is a response packet for reading a MemoryRead read request.

For Completion and Memory Write packets, bits 9: 0 of the first word of the packet indicate the length of the payload field of the packet.

If “0000000000” is indicated, this is interpreted as “10000000000”, that is, the length of the Payload package in this case is 1024 words.

1024 words is the maximum possible length of a Payload packet of type Completion and Memory Write.

Package format Memory Write 3DW.

The format of the package is Memory Write 4DW.

Packages of type MemoryWrite are used to write information to the device on the I-Bus. The Address field of the packet contains the address of the device into which information is to be written. Accordingly, packets of the type MemoryWrite 3 DW use 32-bit addressing, and packets of the type MemoryWrite 4 DW use 64-bit addressing.

Data is transmitted in packets in a frame structure. The frame structure is a set of packets or one packet (in the case when the amount of transmitted data is not more than the maximum possible packet length according to the data (Payload) taking into account service words). In this case, the first packet of the frame should contain a sign of the beginning of the frame, and the last packet - a sign of the end of the frame. Also, each packet in the frame structure contains a color field that determines the source of the incoming data, or, ultimately, the data destination of this frame. Thus, thanks to the color field, the device on the I-Bus can differentiate the transmission or reception of up to 1024 different data arrays. The frame structure in the packet basis is shown below.

The format of the package is Memory Write 4DW. Frame structure.

Package “Memory Write 4DW. Framestructure ”(“ data transfer in the frame structure ”) differs from the usual package“ Memory Write 4DW ”in that there are two service words after the header. These 2 words do not refer to the packet header, but to its Payload, therefore the Payload length (Length in bits 9: 0 of the first packet word) is indicated counting these service words.

The first service word contains:

The sign of the beginning of the SOF frame is the 31st bit - 1 - the packet is the first packet of the frame, 0 - the packet is not the first packet of the frame.

The sign of the end of the EOF frame is the 30th bit - 1 - the packet is the last packet of the frame, 0 - the packet is not the last packet of the frame.

If the entire frame is transmitted in one packet, then in this packet both signs - SOF and EOF - must have the value '1'.

Color - 10-bit color of data in this packet of this frame.

The second service word contains:

Frame Flags - an optional field with error flags and status bits, depending on the specific implementation of the system. The Frame Flags field allows you to control incoming frames with data for the integrity and relevance of the data contained in the received frames. Thanks to this field, the device can diagnose a particular malfunction that arose during operation. The most typical use of the following flags:

- Flag Padding - if the flag contains 1, it means that the given frame was finished off with zeros, i.e. at the expected time of arrival, the required number of words was not received.

- Flag Cutting - if the flag contains 1, it means that the given frame has been cropped, i.e. at the expected time of arrival of the frame, more than the required number of words was taken.

- Flag Frame Missing - if the flag contains 1, this means that this frame contains zeros, i.e. not a single word was received at the expected time of arrival of the frame.

- Flag Frame Structure Error - if the flag contains 1, it means that when receiving this frame there was no packet with the EOF flag, but the next packet with the SOF flag came.

Frame Counter - 15-bit frame counter.

Incremented for each received frame with data.

The use of the Frame Flags and FrameCounter fields is optional and is determined by the device configuration registers on the I-Bus.

For multicasting, use Memory Write 4DW packets with the value ADDRESSLOW (31:28) = "0111". In this case, the ADDRESSLOW address values from 15 to 0 bits are used as a bitmask to determine which devices the multicast packet will go to.

The bottleneck in terms of bandwidth is the lattice of the I-Bus controller, therefore, in the case when neighboring 32-bit words in a packet are addressed to one processor (for example, with 64 bit capacity of incoming data), the second word can be written to the processor in grid bypass. That is, the processor will first receive the first word that passes through the grating, and then the second word that passes bypassing the grating.

Memory Write 4DW packets are also used for the double processing speed mode of the stream, and the controller is switched to double mode by writing the control bit to the configuration register of the I-Bus controller. The essence of the mode is that the data "Payload WordK" and "Payload WordK + 1" (where K = 1, 3, 5, ... N-1) are related, and only the word "Payload WordK" is processed in Lattice, a "Payload WordK + 1", bypassing the handler, is written to the same processor as the word "Payload WordK". Thus, in one clock cycle of processing a data word, two data words are now transferred to processors, and not one.

Package format Memory Write 3DW. Frame structure.

For packages “Memory Write 3DW. Frame structure ”the use of the frame structure is similar to that described above for“ Memory Write 4DW ”packets with the only difference: the second service word (with Frame Flags and Frame_Counter) is present only in the first frame packet (marked with SOF = '1'), all other frame packets contain only one service word (with SOF, EOF and Color).

The use of the frame structure in the transmitted data packets will allow you to bind data to a specific frame (time count), which is important for devices that transmit information in real time. The module on the I-Bus, setting the SOF and EOF bits, as well as accompanying the stream with the frame number, determines where the data of this time interval starts and ends, whether there were frame skips during operation.

All final transmitting and receiving devices must have control of the frame structure for errors in the structure. The following situations must be checked:

- The presence of EOF, if there was SOF. The arrival of a packet with the SOF flag, provided that there was no packet with the EOF flag, should be considered an error situation in which a frame with the signs of an error should be generated (Flags field).

- Checking the required number of data to be received in this frame. If less than the specified number of data words has arrived, the frame must be supplemented to preserve the structure of the processed information, and the Flag Padding flag will be set in the Flags field. If more than the specified number of data words has arrived, the frame should be cropped, and the Flag Cutting flag will be set in the Flags field.

- Checking the receipt of data. If no data packets have arrived at the specified time interval, an “empty” frame must be formed with zeros filled with the specified size, and the Flag Frame Missing flag will be set in the Flags field.

Claims (1)

A method of transmitting information, characterized in that information in the format of PCI-Express packets is transmitted both through serial high-speed communication channels and through a parallel bus, and, depending on the address in the packet, data is redirected either inside the I-Bus controller or to an external one PCI-Express bus and then through the PCI-Express switch and to other I-Bus controllers, while the PCI-Express switch is configured to transmit a packet simultaneously to several I-Bus controllers, the I-Bus controller is configured to work in double mode the speed of processing the stream, and preliminarily, the number of necessary terminal stations and switches is determined with the necessary topology of the communication channels between them, using the configuration packets transmitted through the used communication channels, the used switches and terminal devices are used to receive / transmit information, the transmitted information is divided into packets for transmission according to the PCI-Express standard with the size of useful data not exceeding 4 kilobytes, with each packet consisting of a header and data fields, intended also for recording transmitted information, the header contains information about the type of packet, the sender address of the packet and the address of the receiver, PCI-Express levels are used as the data exchange format, namely: Physical Layer, Data Link Layer , Transaction Layer.

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