JPS5813044A - Delay lock loop - Google Patents

Abstract

PURPOSE:To obtain a delay lock loop with an improve S/N ratio by dividing tap outputs of a received signal delay line into a preceding and a trailing group, and corelating these groups each other, and then obtaining a maximum output when all tap outputs are synthesized. CONSTITUTION:An M-series signal of a carrier band after two-phase phase modulation is inputted to a receiving terminal 102, and delayed through a delay line 200 with taps by one chip for every tap. On the other hand, an M-series generator 270 generates the same series as the signal series of a diffusion code generator on a transmission side, and the output and respective tap outputs of the delay line 200 are inputted to correlators 211-215. The outputs of the correlators 211-213 are summed up by an adder 220, and outputs of the correlators 214 and 215 are also summed up by an adder 230. The difference between the outputs of both the adders is outputted from a subtracter 240 and smoothed by a loop filter 250 to control a voltage-controlled oscillator 260 by its output, thereby supplying the output of the oscillator as a clock signal for the M-series generator 270.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a delay lock loop used for Kf to synchronize code sequences.

Conventionally, in the direct spread spectrum communication system, etc., in order to synchronize codes on the receiving side, a large-length sequence code generator that generates the same sequence of codes as the spreading code generator used on the transmitting side is used. A delay lock loop is used to determine the point at which the correlation between the output code of a particular stage of the code generator and the received signal is maximum.

A conventional delay lock loop is configured as shown in FIG. 1, for example. That is, expressed as ±1, 7
'c Binary maximum flame sequence code (hereinafter referred to as M sequence) is input to terminal 1OOK accompanied by noise such as white noise. Then, the output signal of the ON stage of the M sequence generator 50 (± expressed as l) and the input signal by a multiplier l
Multiply by O. Further, the output signal of the M-sequence generator 50ON-2nd stage and the input signal are multiplied by the multiplier 11, and the difference between the absolute values of the outputs of the multiplier 11 and 100 is calculated by the subtracter 20.
Output from. The output of the subtracter 20 is sent to the loop filter 3
It is smoothed by 0 and used as a control input for the voltage controlled oscillator 400. The oscillation frequency of the voltage controlled oscillator 40 is controlled by the output voltage of the loop filter 30, and its output signal is used as the clock signal of the M-sequence generator. Like this tk
In the f-erasure lock, if the output sequence of the N-th stage is P, and the output sequence of the N-2nd stage is PIJ, the output of the loop filter 30 is the correlation value between the received signal and 8. This indicates the difference in the correlation value between the received signal and &-2. Assuming that the integration time of each bit of the spreading code generated from the spreading code generator on the transmitting side is τt - 1 chip, for example, the phase of the above P and the received signal is more than 1 chip apart': If it is good, the correlation is The value will be 0, and the maximum value will be reached when there is an exact match.

Considering that P*-t is maximum at a phase 2 chips away from it, the output of the loop filter 30 has a phase error of -τ
It takes a positive maximum value when the phase error is 10τ, a negative maximum value when the phase error is 127, and becomes zero when the phase error becomes 127 or more (see FIG. 2(a)).

Also, when the phase error is 00, it becomes exactly zero.

When the phase error is 00, the output signal of the N-1st stage and the received signal are synchronized. That is, the correlation between the output signal of the N-1st stage and the received signal is K as shown in FIG. 2(b). As understood from the above, if the oscillation frequency of the voltage controlled oscillator 40 is controlled so that the output of the loop filter 30 becomes 0, the output phase of the M-sequence generator 50 can be controlled to a constant value and synchronized. I can do it. The delay lock mentioned above
For loops, J. J., 5pilker, J.
r, ”' Delay-LockTracking
of Binary Signals”
IEEE Transactionson 5pa
c@Electronics and Telemet
ry 1963 March, please refer to Tameya.

The above-mentioned delay lock loop is used for code synchronization in normal direct sequence spread spectrum communication. Even in a transmission path where there is so-called multipath fading, if the delay difference between paths is 1 chip or more, each path exhibits independent correlation characteristics, and the delay lock loop becomes - A loop is said to have the advantage of locking onto only one path and being unaffected by signals from other paths. However, if you look at it differently, this means 1.
It has the disadvantage that it uses only the received signal energy from one path, and is a delay-locked loop trap that is vulnerable to noise.

The present invention solves the above-mentioned conventional drawbacks and provides a better delay-locked loop that combines the signal energies of all paths.

The delay lock loop of the present invention includes a maximum-series code generator that generates codes of the same series as the transmitting spreading code generator, and a voltage-controlled oscillator that generates a clock signal for the maximum-sequence code generator. a tapped delay line for successively delaying a received signal, each tap output signal of the tapped delay line and an output signal from a particular stage of the maximum-sequential code generator; a first adder that adds outputs of a plurality of correlators corresponding to tags in the preceding stage of the tapped delay line among the plurality of correlators; a second adder that adds the outputs of the plurality of correlators corresponding to the taps in the subsequent stage; a subtracter that takes the difference between the outputs of the first adder and the second adder; and a subtracter that smoothes the output of the subtracter. and a loop filter, and the oscillation frequency of the voltage controlled oscillator is controlled by the output of the loop filter.

gK, The present invention will be explained in detail with reference to the drawings.

FIG. 3 is a block diagram showing one embodiment of the present invention.

That is, a signal of the next carrier band that has been subjected to two-phase phase modulation in the M sequence is input to the reception terminal 102.
By 1 tatsugu a! Delay by tkL1 chip.

In this embodiment, the tapped delay line 200 is constructed by cascading delay circuits 201 to 204 for one minute. On the other hand, the M-sequence generator 270 generates the same code sequence as the spreading code generator on the transmitting side, and the cough output and the delay line 2
00 and the correlators 211 to 21, respectively.
5. A first adder 220 adds the outputs of the correlators 211 to 213, and a second adder 230 adds the outputs of the correlators 214 to 215. Then, the difference between the outputs of the adders 22G and 230 is output from the subtracter 240 and smoothed by the loop filter 250. The oscillation frequency of the voltage controlled oscillator 260 is controlled by the output voltage of the loop filter 250, and the output clock of the oscillator 260 is provided as a clock reference for the M-sequence generator 270.

The correlators 210 to 215 are constructed as shown in FIG. 4. In other words, the tap output of the tagged slow gIa 200 is applied to the multiplier 216 via the input terminal 103, and is multiplied by the output of the M-sequence generator 270, which is also input to the terminal 104. The output of the multiplier 216 is band-limited by a band-pass filter 217, then subjected to envelope detection by an envelope detector 21B, and outputted to a terminal 105. Each correlator outputs a correlation output corresponding to the magnitude of the received signal when the phase of the M sequence in the direct wave or reflected wave in the tap output matches the phase of the M sequence output from the M sequence generator 270. .

FIGS. 5(1) to (e) #'i show the output characteristics of the correlators 211 to 215 when the phase of the M sequence generator 2700 is changed when only one direct wave is being received. Further, FIG. 5<i) shows the characteristics of the first adder 220, and FIG.
) indicates the output characteristics of the second adder 230. That is, FIG. 5(f) is a composite of nine characteristics from <8) to (C) in FIG.

Therefore, the output characteristic of the subtracter 240 is as shown in FIG. Therefore, when the oscillation frequency of the voltage controlled oscillator 260 is controlled so that the output of the loop filter 250.1 becomes 0, the sequence output from the M-sequence generator 270 is adjusted to the phase between the intermediate taps of the correlators 213 and 214. will match. When using a delay lock loop using 5 taps as in this example, the signal is detected by 5 taps.
It is normal to add the components of all the taps, and it is desirable that the center tap be the center of correlation. To this end, it is sufficient to input only the outputs of the correlators 211 and 212 to the adder 220. In this case, the first adder 2
Since the output characteristic of 20 is K as shown in Fig. 5(i),
The output characteristics of the subtracter 250 are as shown in (j)K in the figure. Therefore, if the center tap is the center of correlation, the correlator 213 will be able to accurately correlate.

Next, a case will be described in which not only a direct wave but also a plurality of reflected waves tft, . . . are input signals that have passed through detour paths. Now, as shown in FIG. 6(a), if we focus on the direct wave and consider the case where four reflected waves come in with a delay of l chip interval, the output characteristics of the correlators 211 to 215 are as follows. As shown in curves 60 to 64 in FIG. 6(b).

In other words, as the M-sequence generator 270 lags, a correlated output with the reflected wave following the main signal occurs, so it exhibits a scalene triangular characteristic with a gradual downward curve from the maximum output value. . Of course, the peak position of each correlator is shifted by l chip. Therefore, the output characteristics of adder 220 are:
The song in Figure 6 (C)! 7 (1m is indicated, adder 2
30 is shown by curve 71 in the figure. As a result, the output characteristics of the subtracters 2 and 40 are the curve 8o in FIG.
It becomes as shown in . At this time, the total output of all correlators becomes as shown in curve 81 in the figure, so if the received signal obtained by combining all the tap outputs is demodulated with the M sequence of phase locked by the 0 intersection of curve 8o, almost the maximum reception can be achieved. Electricity can be used. However, since the peak on the + side of song 1180 in the figure is slightly lower than the peak on the -A side, it is desired that the supplementary characteristics be improved a little. Now, if only the correlators 211 and 212 are input to the first adder 220, the output characteristic of the first adder 220 will be as shown by the curve 90 in FIG. 6(e). The output of the second adder 230 becomes like the curve 91 in the same figure, as described above. Therefore, the output characteristics of the loop filter 250 are as shown in the curve 892 of FIG.
The value of the mountain on the + side becomes higher. That is, the complementary properties are improved. In this case, the zero intersection of the curve 92 is shown in FIG. 6(d).
Although the phase corresponding to the maximum peak of the curve 81 is considerably shifted by p, the decrease from the maximum peak value is slight. In general, the size of reflected waves is not fixed and varies depending on the transmission path, so it is difficult to find an optimal synthesis method. It is better to combine using an adder. If a received signal obtained by combining all the tap outputs is demodulated using the M sequence generated in such a delay lock loop, it can be decoded with approximately the maximum received power.

In the above-described embodiment, the tap interval is set to 1 chip, but the tap interval does not necessarily have to be 1 chip. Further, each tap interval does not necessarily have to be constant. Partially as in the case described in FIG. 6(e). , Tsubu Seki,,
'l=etc.), the capture characteristics may be improved by making the spacing larger than the protrusion spacing. In short, by dividing a plurality of tap outputs into the first half and the second half and correlating them, it is possible to construct a delay lock loop that can obtain approximately the maximum output when all the tap outputs are combined. ,Also,
The signal-to-noise ratio of the loop itself is also lower than that of traditional delay locks.
It can be a big improvement over loops.

As described above, in the present invention, in a transmission path where a plurality of reflected waves arrive, the energy of all the reflected waves is configured to be synchronized with a received signal that is synthesized.・A lock loop can be provided.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a conventional delay lock loop, FIG. 2 is a diagram showing correlation characteristics of the conventional example, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. The figure is a block diagram showing an example of the correlator used in the above embodiment, Figure 5 is a diagram showing the correlation characteristics of the main parts of the Kamimachi% embodiment when there is no reflected wave, and Figure 6 is the above actual result when there are multiple reflected waves.
(It is a diagram showing the correlation characteristics of each main part of the nine embodiments. In the diagram, 200...tapped delay line, 201 to 2
04...Delay circuit, 21o...Correlator group, 2°11
~215-correlator, 216... multiplier, 217...
Bandpass filter, 218... Envelope detector, 22o...
・First adder, 23o...Second adder, 240...
Subtractor, 250...Loop filter, 26o...Voltage controlled oscillator, 270...M sequence generator. Agent Patent Attorney Sumi 1) Shun So No. 1 ji 1 Figure 4 γ] 4 Figure 5 ta 147 A ■

Claims (1)

[Claims] In a delay-locked loop comprising a maximum flame sequence code generator that generates a code of the same sequence as the transmitting side spreading code generator, and a voltage controlled oscillator that generates a clock signal for the maximum flame sequence code generator, a tapped delay line that sequentially delays a received signal; and a plurality of correlators that correlate each tap output signal of the tapped delay line with an output signal from a specific stage of the maximum flame sequence code generator. , a first adder that adds the outputs of a plurality of correlators corresponding to the taps at the front stage of the tapped delay line among the plurality of correlators; and a plurality of correlators corresponding to the tags at the rear stage of the tapped delay line. a second adder for adding the outputs of the adders; a subtracter for taking the difference between the outputs of the first adder and the second adder; and a loop filter for smoothing the output of the adder and the second adder. A delay lock loop whose purpose is to control the oscillation frequency of the voltage controlled oscillator by the output of the loop filter.