JPS60229544A - Synchronization system of two-way digital communication system - Google Patents

Abstract

PURPOSE:To attain synchronous acquisition securely at a high speed by multiplying a bit clock regenerated from the digital information of a down circuit by specific times and generating a clock signal, and using this clock signal as a synchronizing signal for at least either of the data of an up circuit and a pseudo noise code sequence. CONSTITUTION:An input signal is demodulated by a demodulator 61 at a terminal side 52 and its demodulation output is supplied to a level discrimination circuit 62 and also supplied to a bit clock regenerator 63. Then, the bit clock regenerator 63 regenerates the bit clock of frequency fb from the demodulation output and supplies this bit clock as sampling pulses to a level discrimination circuit 63 to discriminate on ''1'' or ''0'' on the basis of those sampling pulses when an eye pattern is opened most, leading desired down data out to the side of an output terminal 64. Further, the bit clock is supplied from the bit clock regenerator 63 to a frequency divider 65 at the terminal side 52 and multiplied by a specific multiple of the frequency of the bit clock to generate the clock signal, which is supplied as the synchronizing signal to a PN code generator 66.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to a synchronization system for a bidirectional digital communication system suitable for use when transmitting digital information in both directions.

Background technology and its problems In the bidirectional communication system, the center (?J(
Information is transmitted from the station side to each terminal side via the downlink (Down-Link), and each terminal side transmits information via the uplink line (IJ
Information is sent to the center side via I')-Link).

Figure 1 shows an example of such a seed coat direction digital communication system. In the figure, 011 is the center side, O3 is the terminal side, and the center side 01) is provided with a clock generator. , a pit clock from this clock generator (131) is supplied to the data generation source 0, and data is extracted based on this pit clock and supplied to the modulator IIs as downstream data.
After receiving modulation based on a predetermined modulation method such as , FSK or ASK, the high-pass band section 1 of the bandpass filter 061 (
1), via the transmission cable an, and further through the bandpass filter 0F3 (high-pass band section H) to the terminal side O3.

On the terminal side α2, the input signal is demodulated by the demodulator 09, and the demodulated output is supplied to the level discriminator circuit (2) and also to the bit clock regenerator Qυ. Then, the bit clock regenerator +213 regenerates the sibit clock from the demodulated output, and supplies this pit clock as a sampling pulse to the level discrimination circuit ■. 1'' and 0'' are determined, and the desired lower side data is taken out to the output terminal Q2 side.

In addition, on the terminal side (12+), data from the input terminal (23) is supplied to one input terminal of the multiplier 24, and pseudo noise (hereinafter referred to as PN) from the code generator Q9 is supplied to the other input terminal. PN code is supplied to the terminal 061 in synchronization with a clock signal from a crystal oscillator (not shown);
This causes the data to be spread spectrum and extracted.

The main reason for spreading the spectrum of data on the terminal side (121) is to prevent the deterioration of characteristics such as the S/N ratio of upstream data from the terminal side to the center side due to the heat generation of the terminal resistor etc. at the terminal side pressure. Therefore, as will be described later, the reception section on the center side despreads the received data using the same PN code used in the transmission section on the terminal side to reproduce the original data.

The spread data from the multiplier (2) is fed to a modulator (5) where it is subjected to PSK modulation, for example, and then passed through a bandpass filter 0.
81 (low pass band part L), and further passes through the transmission cable 0.71 and the low pass band part L of band filter 061 (low pass band part L).
), in other words, it is sent back to the center side (old) via the uplink.

Note that information sent on the downlink is usually transmitted using a higher frequency band than the uplink, for example, 50 to 450 MHz.
On the other hand, the information sent on the downlink is lower than that on the one-to-one link, for example, 5
~30M! (Transmission is performed using the frequency band z.

The data transmitted from the terminal a2 is supplied to one input side of the multiplier (c) and also to the delay lock loop circuit (c). This delay lock loop circuit (29 uses two correlators to which two local reference code sequences, which are equal in phase but one delayed than the other, are input; that is, a delay lock loop circuit (c)
In , a multiplier (
), ・F device filter Ca1l, detector c3z
and a multiplier (g) as a correlator forming the second sequence,
A bandpass filter . And the detector oz
. Then, the contents of a shift register (not shown) forming the PN code generator ell are sequentially shifted by the clock signal from this oscillator (to), and are directly supplied as is to the other input terminal of the multiplier (to). , the other input of the multiplier α is supplied via a 1-bit shift circuit.

In the multiplier (to), the data from the bandpass filter a and PN
The PN code from the code generator is multiplied, that is, despread is performed, and the multiplication output passes through a bandpass filter 01) and is supplied to the detector cl'lJK. As a result, the detector 025
As shown in FIG. 2A, a triangular signal Sl having a width of 2 bits is obtained on the output side. In other words, the position of the signal S0 is where the correlation function between the encoded input signal and the local reference code sequence is obtained. In addition, in the multiplier field, the data from the bandpass filter (16+) is multiplied by the shift circuit (PN code shifted by 1 bit by 40) from the PN code generator, and the multiplication output passes through the bandpass filter to the detector (to the detector). ).As a result, on the output side of the detector (to), K is obtained as shown in FIG. 2B, and a signal S2 obtained by shifting the signal S1 in FIG. 2A by 1 bit is obtained. These two signals S1 and S2, which are generally correlator outputs, have the same correlation function, but their correlation peaks are offset by an amount equal to the delay between the local reference signals, that is, in this case, they are offset by one bit. Therefore, the composite correlation function of the delayed Loclusot circuit is bipeak triangular.

That is, a signal S3 as shown in FIG. 2C is obtained at the output side of the comparator. There is a portion where the correlation function is linear between the midpoints of both peaks of this bipeak triangular shape. In other words, the midpoint is where the autocorrelation function is taken, and is the lock point of the delay lock loop circuit (c).

Since the two local reference code sequences of this delay lock roots circuit (toward) are offset by half the amount of delay between them and track the input r-time, more than half of the correlation peak value To achieve this, it is necessary to reduce the delay to one bit or less. Therefore, this delay lock loop circuit -
The output of the PN code generator G1 is supplied to the other input side of the multiplier (c) via the lA bit shift circuit (41). At this time, the output side of the bit shift circuit (411) receives a signal S4 as shown in the second diagram.
is obtained.

The signal thus obtained at the output side of the multiplier (2) is supplied to a demodulator (43) using, for example, a Costas loop circuit (manufactured by Kostas Loop Co., Ltd.) through a band/base filter +4'lJ, where it is demodulated.

The demodulated signal from the demodulator a3 is supplied to the level discrimination circuit 04) and also supplied to the pit clock regenerators (4).Then, as mentioned above, the bit clock regenerator (4 regenerates the pit clock from the demodulated output) Then, this pit clock is used as a sampling pulse for the level discrimination circuit θ4)
Based on this sampling pulse, "1" or "0" is determined at the most open part of the eye pattern, and the desired upstream data is extracted to the output terminal (46) side. .

By the way, in the case of a conventional circuit with such a circuit configuration,
As mentioned above, the phase of the PN code, which is generated in the receiving section on the center side and is the same as that on the transmitting section on the terminal side, is slightly varied, the correlation between the inner codes is calculated, the peak is detected, and the synchronization search process is started at the point where the peak is detected. After that, tracking is performed using a delay lock loop (c) to prevent the inner code sequence from going out of synchronization. Therefore, for example, if the inner code sequence becomes out of synchronization due to external noise, etc. It is necessary to repeat the process of synchronization search and tracking from the beginning, which has the disadvantage that synchronization acquisition is uncertain and takes a long time.

OBJECTS OF THE INVENTION The present invention has been made in view of the above problems, and provides a synchronization method for a bidirectional digital communication system that allows reliable synchronization acquisition in a short period of time.

Summary of the Invention In this invention, in a bidirectional digital communication system in which at least uplink data is spread spectrum and transmitted using a pseudo-noise code, a pit clock reproduced from downlink digital information is multiplied by a predetermined value. A clock signal is formed, and the clock signal is used as a synchronization signal for at least one of the data or pseudo-noise code series on the above-mentioned upper line. Therefore, in the present invention, reliable and high-speed synchronization acquisition can be obtained.

EXAMPLE Hereinafter, an example of the present invention will be described in detail based on FIGS. 3 to 8.

FIG. 3 shows the circuit configuration of this embodiment. In the figure, 61) is on the center side, l! +3 is on the terminal side.

The transmitter on the center side 611 is provided with a data sequence generator 63) and a frame synchronization generator 6541, and the data sequence generator 5S as shown in FIG. 4DK and the frame synchronization generator 64 as shown in FIG. The frame synchronization signal shown in C is generated from five timing signal generation circuits t in FIG. 4A.
The signal is extracted by a pit clock having a frequency fl) as shown in FIG. A signal as shown in FIG. 4B is derived and supplied to a modulator 67).

And here, for example, FSK, FSK or Vi, As
After being modulated based on a predetermined modulation method such as K, the signal passes through band filter 6 (high pass band section 11), via transmission cable 69, and then passes through band filter i4 (high pass band section H). and is supplied to the terminal side 52.

On the terminal side 152, the input signal is demodulated by a demodulator El), and the demodulated output is supplied to a level discrimination circuit and also to a pit clock regenerator 13. Then, in the pit clock regenerator I■, the frequency f is determined from the demodulated output.
1) is regenerated, this pit clock is supplied as a sampling pulse to the level discrimination circuit, and based on this sampling pulse, Aino ("1" at the widest point of the turn) is reproduced. ”, “0”, and output the desired downlink data (Fig. 6A) to the output terminal 64) side.
).

In addition, on the terminal side 2, the pit clock from the pit clock reproduction amount is supplied to the frequency divider iK, and the frequency of the bit clock is multiplied by a predetermined time, for example, -" (where m and nm are integers) to have a frequency of - x fb. A clock signal is generated and supplied as a synchronization signal to the PNN code generator.

Here, as the branch station Masuda, for example, one having a phase lock loop (PLL) configuration as shown in FIG. 5 is used. That is, the bit clock of frequency fb from the input terminal (65a) connected to the bit clock reproduction amount side is divided by a divider (65b), for example, to -, and the frequency is set to f.
After making the signal b/m, it is supplied to one input side of the phase comparator (65C). Also, this phase comparator (65c)
On the other input side of ) is converted into DC voltage through a low-pass filter (65d), and this DC voltage is sent to the oscillator (65d).
65e), the oscillation frequency of which is controlled according to the error, and outputted to an output terminal (65g) connected to the PNN code generator side. In other words, the output terminal (6
When PLL is synchronized on the sg) side, the frequency fb of the signal supplied to each input side of the phase comparator (65C)
/m and f. Since ut/n is equal, the frequency 'out
An output signal with a frequency of ``--X fb is taken out. Then, this output signal g is supplied to the PN code generator port. At the output side of 151, a lock signal having a frequency of f b/2 as shown in FIG. 6C is supplied as a synchronizing signal to a PN code generator.

Assuming that an M-sequence generator is used for the PNN code generator, the longest sequence length of the M-sequence generator is generally 2n-1 bits, where n is the number of stages of the shift register. . Incidentally, the M-sequence generator is combined with a shift register (not shown) consisting of three stages of D-type flip-flop circuits, and a logic circuit that feeds back the logical combination of the states of each stage to the input of the shift register. It is assumed that the circuit is constituted by an exclusive OR (hereinafter referred to as EOR) circuit, and one cycle generates an M sequence with a period of 7, for example, [1]o1oo], as shown in Figure 6. The PN code generator [6] sequentially shifts the contents of its shift register in synchronization with a clock signal, which is a synchronization signal from the frequency divider mill, so that one cycle has a pattern as shown in Figure 6. A PN code will be generated.

The PN code from the PN code generator is supplied to one input terminal of the multiplier η, and data is supplied from the input terminal to the other input terminal of the multiplier, and both are multiplied. . The data is spectrum spread using a PN code.

The multiplication output from the multiplier 6η is supplied to the modulator -, where it is subjected to, for example, PSK modulation, passes through a bandpass filter (the low-pass band part L), and is further transmitted to the transmission cable +5! It is sent back to the center side αυ receiving unit via I and the bandpass filter 6 frame (low-pass band part L) 2, that is, via the uplink.

The upper si data passed through the bandpass filter (2υ (low-pass part L)) is fed to one input of a multiplier σQ, and is also fed to the other input of this multiplier σ0 as will be explained in detail later. A PN code is supplied, and the transmitted data is subjected to spectrum despreading using this PN'$+ code.The output of this multiplier is then supplied to a demodulator συ, where it is demodulated. The demodulated output is level discriminator σ
"1" based on the bit clock regenerated from the demodulated output in the pit clock regenerator σj,
A determination of "O" is made, and the signal is output as digital information to the output terminal ff41.

On the other hand, the receiving section on the center side 51) is provided with a PN code generator σ9 consisting of a shift register (75a) and an EOR circuit (75b) similar to the PNN code generator on the terminal side, and this PN code generator ff! 19 is a controller (7 (from 9K) 3-bit !reset information based on the frame synchronization and loss as shown in FIG.
are preset to preset terminals A, B, and C of.

This controller 6e is a level detector (7'0) provided on the output side of the multiplier plane.

The preset information given to B and C is stored in the memory σ8 as address information for the next polling, corresponding to each terminal.

Next time, by taking out the address information from this memory 6υ and giving it to the shift register (75a) to preset this shift register (75a),
The time required for synchronization acquisition is reduced. Note that the shift register (75a) is shifted by a clock signal having a frequency of 1×fb from six timing signal generation circuits, so that its output terminal Q
3, a PN signal as shown in FIG. 7A is extracted. In addition, in order to make the propagation delay between the center and terminals random, it is necessary to match not only the PN code sequence but also the fine phase of the PN code (the time delay of the PN code sequence corresponding to the delay time). be. Therefore, on the output side of the shift register (75a), a shift register 69 consisting of a four-stage D-type flip-flop circuit (not shown) is further provided.
is provided. This shift register n σ91 is □・fb from the timing signal generation circuit (to)
is shifted by a clock signal having a frequency of .

And its output terminals Q1 r Q2 , Q3 and Q4
The respective outputs as shown in FIGS. 7B, C, D, and E, that is, outputs shifted in units of 1/4 bit, are supplied to a switch circuit. This switch circuit (a) has a preset terminal and E like the shift register (75a), and after being reset by the controller σe, it is switched based on the preset address information.

Therefore, for the spread tram spread wave supplied to one input terminal of the multiplier ff(e), the switch circuit is connected to the controller σe.
The phase of the PN code is shifted as shown in FIG. The output of the detector σO is detected by the level detector ση, and when the level reaches the maximum, the shift register (7
The values of the preset information for 5a) and the switch circuit - are stored in the memory σ under the control of the controller ffE9 as address information from the next polling in correspondence with each terminal.

After performing this procedure on all terminals, the next step is l? - At the time of IJ, the address information is set from the memory information in the shift register (75a) and the switch circuit by the controller QO, and the PN code from the switch circuit taken out as described above and the data from the terminal side are Multiplying is performed using multiplier σC.

That is, each terminal stores the PN code sequence in the same memory σα as the combined PN code, and delays it by a certain phase difference to match the data and multiplication from the terminal side. As a result, real-time synchronization is substantially possible and the time required for synchronization acquisition is shortened.

As mentioned above, the phase of the PN code can be controlled in 1/4 bit units, but the maximum correlation loss CLmax at that time is K 20 log (1-also=1.15) as shown in FIG.
There is no particular problem with the loss of (1.15 dB).

In the above embodiment, the clock signal from the frequency divider is used as a synchronization signal for generating a PN code sequence, but if the data supplied from the input terminal is a digital signal, , this may be used as a synchronization signal for extraction.

Furthermore, the above-described synchronization acquisition and writing of the PN code sequence and its phase into the memory may be performed several times per - day in order to compensate for changes in delay time due to external requirements such as temperature.

In this way, in this embodiment, the clock signal obtained by multiplying the pit clock reproduced by the receiving section on the terminal side by n/m is used as at least one synchronization signal for generating a PN code sequence or extracting data. Therefore, on the center side, once synchronization acquisition is achieved, the clock signal of the received signal is substantially synchronized with the clock signal on the center side, and the received code sequence, that is, the PN code sequence and local code sequence in the transmitter on the terminal side. In other words, the time positional relationship of the PN code sequences in the center-side receiving section is constant. Therefore, even if a temporary loss of synchronization occurs during reception, as long as the local code is generated in synchronization with the transmission clock, the original state will be restored and the synchronization relationship will be maintained. There is no need to redo the search.

Effects of the Invention As described above, according to the present invention, a bit clock reproduced from downlink digital information is reproduced and multiplied by a predetermined value to form a clock signal, and this clock signal is used as a data or pseudo-noise sequence in the uplink. Since at least one of the synchronization signals is used, quick and reliable synchronization acquisition is possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a conventional system, FIG. 2 is a diagram for explaining the operation of FIG. 1, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a signal waveform diagram for explaining the operation, FIG. 5 is a block diagram showing an example of a frequency divider, and FIGS. 6 to 8 are signal waveform diagrams for explaining the operation of FIG. 3. be.

Claims (1)

[Claims] In a bidirectional digital communication system that transmits at least uplink data by spreading the spectrum using a pseudo-noise code, a clock signal is formed by multiplying a pit clock reproduced from downlink digital information by a predetermined value. A synchronization system for a two-way digital communication system, characterized in that the clock signal is used as a synchronization signal for at least one of data or pseudo-noise sequences in the uplink.