JPS58122761A - Resin sealed type semiconductor device - Google Patents
Resin sealed type semiconductor deviceInfo
- Publication number
- JPS58122761A JPS58122761A JP470482A JP470482A JPS58122761A JP S58122761 A JPS58122761 A JP S58122761A JP 470482 A JP470482 A JP 470482A JP 470482 A JP470482 A JP 470482A JP S58122761 A JPS58122761 A JP S58122761A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- semiconductor device
- plate
- lead frame
- sealed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
発明の技術分野
この発明は、ノ臂ターン形成されたチップが樹脂製の外
囲器に封止されて完成される樹脂封止型半導体装置に関
する。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a resin-sealed semiconductor device which is completed by sealing a chip formed with an arm turn in a resin envelope.
発明の技術的背景
一般に、樹脂封止による半導体／譬ツケージは低フスト
で、を九量産に適するといった特徴から広く用いられて
いる。第１図（ａ） ｅ （ｂ）はその構成を示すもの
で、（ａ）図は斜視図、（ｂ）図は（ａ）図のムーム′
總に沿った断面構成図である０図において、１１紘工Ｉ
キシ樹脂等の樹脂封止層、１２線リード、ＪＪはチッ１
．１４はｆンディングワイヤ、ＩＪはマウント基板であ
る。Technical Background of the Invention In general, resin-encapsulated semiconductors/simulators are widely used because of their low fuse and suitability for mass production. Figures 1(a) and 1(b) show its configuration; (a) is a perspective view, and (b) is the muum' of (a).
In Figure 0, which is a cross-sectional configuration diagram along the line, 11 Hiroko I
Resin sealing layer such as xy resin, 12 wire lead, JJ is chip 1
．． Reference numeral 14 indicates an f-landing wire, and IJ indicates a mounting board.
背景技術の問題点
ところで、上記第１図の樹脂封止型半導体装置では、半
導体素子部および接続リード部を樹脂封止する際、樹脂
の注入圧力によシ接続９−ド１１およびがンディングワ
イヤ１４に応力が加わることＫなる。その結果、！ラン
ト基板ＩＪが樹脂の射出圧力で上下に浮き沈みし、ぎン
ディ／グワイヤ１４の剥離あるいは切断というた不良が
発生する。また、接続リード１２の数が多い場合には、
リード間の短絡が発生する勢の欠点があった。Problems with the Background Art Incidentally, in the resin-sealed semiconductor device shown in FIG. This means that stress is applied to 14. the result,! The runt substrate IJ rises and falls up and down due to the resin injection pressure, and defects such as peeling or cutting of the wire/wire 14 occur. In addition, when the number of connection leads 12 is large,
There was a drawback that short circuits could occur between the leads.
発明の目的
この発明は上記のような事情に鑑みてなされた４ので、
その目的とするところは、半導体素子マウント基板の浮
き沈みｋよゐ一ンディンダワイヤの剥離および切断の発
生を防止モき、更Ｋｍ続リード相互の接触による短絡を
も回避し得る信頼性の高い樹脂封止型半導体装置を提供
する仁とである。Purpose of the Invention This invention was made in view of the above circumstances4.
The purpose of this is to prevent the occurrence of peeling and cutting of the lead wires due to the ups and downs of the semiconductor element mounting board, and also to create a highly reliable resin seal that can avoid short circuits caused by contact between leads connected to each other. and Jin, which provides semiconductor devices.
発明の概要
すなわち、この発明においては、チッｆ搭載面の裏ａｉ
Ｋマウ／ト基板の浮き沈みを防止するための合成樹脂板
製の支持部材を設けたものである。Summary of the invention That is, in this invention, the rear ai of the chip mounting surface
A supporting member made of a synthetic resin plate is provided to prevent the K-mount/mount board from floating up and down.
発明の実施例
以下、この発明の一実施例につ匹て図面を参照して説明
する。第２図はその断面構成を示すもので、この発明に
おいては、第１図（ｂ） ｏ構成に加えて合成樹脂板製
の支持部材１ｇｔチップ搭載面１１の裏面と９− Ｙ
７レーム１２と０間に設けたものである。Embodiment of the Invention An embodiment of the invention will be described below with reference to the drawings. FIG. 2 shows its cross-sectional configuration, and in this invention, in addition to the configuration shown in FIG.
It is provided between 7 frames 12 and 0.
上述した樹脂封止型半導体装置の形成方法状、まず、リ
ードフレーム１２のマウント基板（チトシ、ワイヤ−ン
ディングを行なう。次に１例えばテフロンコートした熱
板上に合成樹脂板１＃を設置して加熱後、リードフレー
ムＩｌｔ搭載して合成樹脂板１６とリード７レー五１２
とを接着固定し、これを樹脂で被覆して封止し完成する
。The method for forming the above-mentioned resin-sealed semiconductor device is as follows: First, the lead frame 12 is mounted on a mounting board and wired. Next, for example, a synthetic resin plate #1 is placed on a Teflon-coated heating plate. After heating, the lead frame Ilt is mounted and the synthetic resin plate 16 and leads 7 and 5 12 are mounted.
This is completed by adhering and fixing and covering and sealing with resin.
なお、上記工程において、リードフレーム１１と合成樹
脂板１６ｔ−予め接着固定してから素子のマウントおよ
びがンディングを行なっても良いの紘もちろんである。In the above process, it is of course possible to bond and fix the lead frame 11 and the synthetic resin plate 16t in advance before mounting and bonding the element.
また、合成樹脂板１−は樹脂封止層と同じ樹脂で形成し
ても良い。Further, the synthetic resin plate 1- may be formed of the same resin as the resin sealing layer.
このような構成によれば、樹脂封止時の注入圧力による
半導体素子マウント基板の浮き沈みがないので、ｌンデ
ィングワイヤの剥離、切断あるいは接触による短絡の不
良を有効に防止することができる。また、マウント基板
と接続リードが固定されているために、取シ扱い時等に
よるがンディングワイヤ相互の接触および接続リード間
の接触がないので短絡を生じることもない。According to such a configuration, the semiconductor element mounting substrate does not rise or fall due to the injection pressure during resin sealing, so it is possible to effectively prevent short circuit defects due to peeling, cutting, or contact of the landing wire. Furthermore, since the mount substrate and the connection leads are fixed, there is no contact between the mounting wires or between the connection leads during handling, so that short circuits do not occur.
第３図は、この発明の他の実施例を示すもので、この・
ヤツケージでは上記合成樹脂板から成る支持部材１−に
加えて、チ、ｆｋｌｌＬり囲む合成樹脂製の枠体Ｊ Ｆ
、 １ Ｆ’を設けたものである。FIG. 3 shows another embodiment of this invention.
In addition to the supporting member 1- made of the above synthetic resin plate, the YA cage also includes a synthetic resin frame JF surrounding the supporting member 1-.
, 1 F'.
このような構成によれば、水分がリードフレームとモー
ルド樹脂との境界面から侵入するのを阻止できるので、
上述し九効果に加えて更に防水性を向上てきるという効
果４得られる。With this configuration, it is possible to prevent moisture from entering through the interface between the lead frame and the molding resin.
In addition to the above-mentioned nine effects, the fourth effect of further improving waterproofness can be obtained.
発明の詳細
な説明したようにこの発明によれば、樹脂封止型の半導
体装置において、封止の際の樹脂注入ｍｌ力による半導
体素子マウント部の浮き沈み管防止できるので、？７デ
インダワイヤの剥離、切断あるいは接触による短絡等の
不ｊｌＬｔ−有効に防止することができる。を九、マウ
ント部と接続り−ｙｇ６が固定されている九めに、取シ
扱い時等によるがンディンダワイヤ相互の接触およびＷ
！続リすド間の接触がないので短絡を生ずることもない
信頼性の高い樹脂封止型半導体装置が得られる。DETAILED DESCRIPTION OF THE INVENTION According to the present invention, in a resin-sealed semiconductor device, it is possible to prevent the semiconductor element mounting portion from floating or sinking due to the resin injection force during sealing. 7. It is possible to effectively prevent short circuits caused by peeling, cutting, or contact of the deender wire. 9. Connect to the mount part - yg6 is fixed.Depending on handling, etc., the wires may come into contact with each other and W
! Since there is no contact between adjacent leads, a highly reliable resin-sealed semiconductor device that does not cause short circuits can be obtained.
第１図（ａ） ＃ （ｂ）Ｆｉそれぞれ従来の樹脂封止
型半導体装ｔを示す斜視図および断面構成図、第２図ｉ
この発明の一実施例に係る樹脂封止型半導体装置の断面
構成図、第３図はこの発明の他の実施例を示す図である
。
１２・・・リード、１５・・・チ、！搭載面、１６・・
・支持部材。
出願人代理人 弁理士 鈴 江 武 彦第１図
（ａ）
第２図
（１））
ＩＩ３図Fig. 1 (a) # (b) Fi is a perspective view and a cross-sectional configuration diagram showing a conventional resin-sealed semiconductor device t, and Fig. 2 i
FIG. 3 is a cross-sectional configuration diagram of a resin-sealed semiconductor device according to an embodiment of the present invention, and is a diagram showing another embodiment of the present invention. 12...lead, 15...chi! Mounting surface, 16...
・Supporting member. Applicant's representative Patent attorney Takehiko Suzue Figure 1 (a) Figure 2 (1)) Figure II3
Claims (2)
いて、半導体素子マウント基板の浮き沈みを防止する九
めの絶縁体の支持部材を設けたこと１−特徴とする樹脂
封止型半導体装置。(1) In a semiconductor device sealed in a resin envelope, a support member made of a ninth insulator is provided to prevent the semiconductor element mounting substrate from floating up and down.1-Characteristics of the resin-sealed semiconductor device .
素子マウント基板におけるチツｆ播１面の裏面とリード
との間に固着されることｔ４１像とする特許請求の範囲
第１項記載の樹脂封止型半導体装置。(2) The support member is made of a synthetic resin plate, and is fixed between the rear surface of the chip f-1 surface and the leads of the semiconductor element mounting board. Resin-sealed semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP470482A JPS58122761A (en) | 1982-01-14 | 1982-01-14 | Resin sealed type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP470482A JPS58122761A (en) | 1982-01-14 | 1982-01-14 | Resin sealed type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58122761A true JPS58122761A (en) | 1983-07-21 |
Family
ID=11591261
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP470482A Pending JPS58122761A (en) | 1982-01-14 | 1982-01-14 | Resin sealed type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58122761A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010031811A (en) * | 2008-07-30 | 2010-02-12 | Fujitsu Ten Ltd | Fuel saving drive diagnosis device, on-vehicle system, drive control device, and fuel saving drive diagnosis program |
-
1982
- 1982-01-14 JP JP470482A patent/JPS58122761A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010031811A (en) * | 2008-07-30 | 2010-02-12 | Fujitsu Ten Ltd | Fuel saving drive diagnosis device, on-vehicle system, drive control device, and fuel saving drive diagnosis program |
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