JPS58121862A - Picture signal editing register - Google Patents

Abstract

PURPOSE:To provide harmony to the arrangement of displayed characters, by providing a means shifting the 1st and the 2nd register groups toward row and column directions cyclicly and a means producing logical sum between the same row and column picture elements of the register groups. CONSTITUTION:Picture information P1 corresponding to a character A is stored in the 1st register group 6, and picture information P2 corresponding to a character 2 is stored in the 2nd register group 7, and when a shift signal S2 is inputted to the group 7 and the position of the characters 2 is adjusted, if picture information P3' as shown in Figure is produced, a overlapped signal Q of logical value 1 is outputted, which represents that the characters A and 2 are overlapped by >=1. Thus, in editing the picture information P3 from the picture information P1 and P2, it is immediately discriminated for the overlapping of the characters A and 2 with the signal Q.

Description

DETAILED DESCRIPTION OF THE INVENTION The present BA relates to an image signal editing register in an image information processing apparatus that performs image information t-editing processing, which is composed of binary pixels arranged in %KrnKrn rows.

The diagram shows the configuration of this type of image information processing system wIr, an example of a word processor. Information P is stored. The processing device 1 extracts image information P corresponding to the character input through operation s2 from the full image information memory 3 and stores it in the register 4,
As shown in FIG. 2, each pixel PE is constructed from pixels PE arranged in m rows and n columns. value 0
The logical value O corresponds to white on the screen of the display unit 5, and the logical value 1#'i corresponds to black on the same screen. Therefore, each image information Pt-configuration The pixel PE group has a configuration of logical values that do not correspond within an m-by-n array and thus represent characters. FIG. 3 is a diagram showing an example of a character string arranged on the screen of the display unit 5. In order to display the character string A squared, first, the corresponding image information Pat-register corresponding to the character A is displayed. 4 and display it on the display section 5, then m rows n/
The image information P corresponding to the character depth made up of the pixel PE group in two columns (hereinafter m rows and n columns will be referred to as full-width, and m rows and n/2 columns will be referred to as half-width) is stored in the register 4 and displayed on the display section 5. to be displayed adjacent to the letter A. In this way, on the screen of display unit 5? The string shown is the letter A and the letter! They may be too far apart and difficult to read.

As is clear from the above explanation, conventional image information processing devices only extract image information composed of full-width or cow-kaku characters in a specified order and display it in an array. The dimensions, especially the width, vary greatly, and the regular arrangement is qJILII! There were times when there was a lack of harmony.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of conventional image information processing devices as described above, and to provide a harmonious arrangement of displayed characters.

This purpose is to provide an image information processing device that edits and processes image information composed of 92-value pixels arranged in m rows and n columns.
a first register group for storing pixels of m' rows and n'columns;
a second register group for accumulating pixels in row 'n' and column 'n'; means for cyclically shifting the first and second registers St in the row direction and column direction, respectively;
l! This is accomplished by providing a means for generating a logical OR of pixels in the same row and column of the two register groups,
In addition to each means, the lsl and the second register group detect one pt of a pixel group of a predetermined logical value included in the image information accumulated by the logical product output of the means. Achieved (by setting up a hand Rt), and
1iii of a predetermined logical value included in the image information stored in the first and 8g2 register groups, respectively, in each of the means;
*Achieved by providing a means Rt for detecting that any one of ct deviates from the area of the first and second register groups o11.Hereinafter, an embodiment of the present invention will be explained with reference to the drawings. O 4th
The figure is a diagram showing an image signal editing register according to one embodiment of the present invention, FIG. 5 is a diagram showing an example of the operation of FIG. 4, and FIG. 6 is a diagram showing another embodiment of the present invention. 0In addition, the same reference numerals indicate the same objects throughout the figures.0 In Fig. 4,
6amlK)n film configuration shift register 61
The second register group 7 is composed of m n-film shift registers 71 to 7m and a selector 70. 6 groups of 1g LUGISTA each
And the second register group 7 is full-width information Pts extracted from the image information memory 8 (Fig. 331). 0 accumulated in
The selector signal S1 is input to the selector 60 or 70, and each shift register 61 to 6mt or 71 to 7m is input.
Furthermore, each of the shift registers 61 to 6 allows the pixel group accumulated in 0 to be shifted cyclically row by row from bottom to top.
By inputting the shift signal S, mt or 71 to 7mK, each of the second register group 6 and the second register group 6 and the second register group I"
F 7 J) Praise the jar ^ Information P is DI to the left L to the stone in units of h! It can be shifted circularly. Furthermore, the pixels PE stored in the corresponding stages 1 to n of the shift registers 61 and 71 to 6m and 7m of the second register #7 and the second register #7 are stored in the gates 811 to 8.
A logical OR is generated for each of m and n. Therefore, the first
The full-width image information P corresponding to the character A as shown in FIG.
When the Gyukaku picture information P1 corresponding to is accumulated, Goo) 8
From 11 to 8mn, full-width image information P in which the logical sum of the two image information PM and the pixels PE existing in the same row and the same column in position P is the pixel PE of the relevant sex and column is output. Mongajo@ps displays the letter AI, which is a superimposed text of the letter A and the letter t, within a full-width space, as shown in FIG. 5, on the -1 side of the display section 5 (FIG. 1). Furthermore, as described above, by inputting the shift signal S or the selector signal S to the second register 7 and the second register 7, the relative position of the letter A and the snow can be adjusted. .

In addition, in the jFs4 diagram, the block register ridge 6 and the second
Corresponding shift registers 61 and 71 of register group 7
Gates 911 to 9 that generate logical product of pixels accumulated in corresponding stages 1 to n of 6Zn and 7m;
The logical AND outputs of the gates 911 to 9mn form an overlapping multi-signal Q via gates 91 to 9m and 9. #The heavy signal Q indicates that among the image information P stored in the register group 6 and the second register group 7, there is at least one pixel PE in the same row and column that has a logical value of 1. For example, it indicates a logical value of 1. Therefore, as described above, the image information P corresponding to the character A is stored in the first register group 6.
I is again a character in the second register group 7! Image information corresponding to P! is stored, a shift signal S! is sent to the second register group 7. When the image information / shown in Fig. 5 is generated while adjusting the position of the letter A and R, an overlapping multi-signal Q with a logical value of 1 is output. Indicates overlap at one or more locations. Above picture information P1 and P
Even when editing the picture information Pst from a, it is possible to immediately identify the stone by using the multi-signal Q in which the letters A and 9 overlap.

More j! In Fig. 46, the logical sum is generated from the outputs of all stages of shift registers 61 and 6m of the fourth register group 6) 101 and 102, and the first stage outputs of all shift registers 61 to 6m. and a gate 103 that generates a logical sum from each n-th stage output.
and 104 are provided. Similar gates are also provided in the second register group 7, but are omitted in FIG. Gates 101 and 102 respectively output boundary signals R and R1 with a logic value of 1 when the image*PI stored in at least 41 stages of the shift registers 61 and 6m has a logic value of 1, and gates 103 and 104 output When the pixel PE stored in at least one of the first stage and nth stage of the shift registers 61 to 6no has a logic value of 1, boundary signals R and R4t of logic value 1 are output, respectively.

Therefore, as described above, with the image information P3 corresponding to the character A stored in the register group 6 and the image information Pg corresponding to the character stored in the second register group 6, the shift signal S is sent to the second register #7. , while adjusting the position of letter A.
When the image information P as shown in the figure is generated, the logical value 1
The boundary signal R4 of 0 is output, and the image information P and P! are 0 or more indicating that the character A is on the boundary of full-width characters. Even when editing image information pgt from the character A and character! Any of these! It becomes possible to immediately identify whether the full-width boundary has been reached or whether the full-width area has been deviated from the boundary signals R1 to R4.

As is clear from the above explanation, according to this embodiment, the letter A
and character 8 are combined into character AI within the same full-width, and the relative positions of character A and the sentence device can be adjusted within the full-width. During this adjustment, if characters overlap each other or if there is a risk of deviation from the full-width area, this can be immediately identified and adjustment can be made easily.

Note that FIGS. 4 to 6 are only one embodiment of the present invention, and for example, the image information P1 and P1 stored in the first register group 6 and the second register group 7 is limited to that shown in the figures. Although many modifications may be made to the previous layer, the effects of the present invention remain unchanged in any case. Further, both the first register group 6 and the second register group 7 are not limited to full-width storage areas, that is, m rows and n columns. The effect of the present invention remains the same even in the case where the register group each has storage areas of m rows and n N columns, but the effect of the present invention does not change. Another example is shown below.Furthermore, it goes without saying that the image information processing apparatus to which the present invention is applied is not limited to the powered word processor shown in FIG.

As described above, according to the present invention, in the image information processing device,
It becomes possible to edit new image information by freely adjusting the relative position of two consecutive pieces of information, and flexible image display becomes possible.

[Brief explanation of drawings]

FIG. 1 is a diagram illustrating the configuration of a word processor which is an example of an image information processing device, FIG. 2 is a diagram illustrating the configuration of image information, FIG. 3 is a diagram illustrating an example of a conventional character arrangement, 4 is a diagram showing an image signal editing register according to one embodiment of the present invention, FIG. 5 is a diagram showing an example of the operation of FIG. 4, and FIG. 6 is a diagram showing an image signal editing register according to another embodiment of the present invention. The diagram shown in FIG. 7 is a diagram showing an example of operation different from that in FIG. 5. In the figure, 1 is a processing device, 2 is an operation unit, 3 is an image information memory, 4 is a register, 5 is a display unit, 6 is a first group of lugistors,
7 is the second register group, 61 to 6m and 71 to 7m
Shift register, 60 and 70 butterfly selector, 811
〜8mn, 911〜9mn, 91〜9m19
and 101 to 104 are gates, PK to P and PFi image information, PE is a pixel, SR is a selector signal, and Sm
is a shift signal, a multi-signal that overlaps Qe-, R1 to R4 are boundary signals, P, 2 Pf P
2 Figure 3 Corpse Figure 4 R2, Figure 6 m x 71 m y n
m X n Akira 7 Figure

Claims (3)

[Claims] (1) In an image information processing device that edits and processes lll1l information composed of binary pixels arranged in rn rows and n columns, a first register group that stores pixels in m' rows and n'columns; “a second register group for accumulating pixels in rows and n# columns; means for cyclically shifting the first and second register groups in the row direction and column direction, respectively; and the first and second register groups; A 1I11 signal 1M collection register characterized by providing means for generating a logical sum of pixels in the same row and column of a group. (2) In an image information processing device that collects and processes image information composed of binary pixels arranged in m columns and n columns, a first register group that stores pixels in m' rows and n'columns; m” line n
a second register group for accumulating the picture
means for generating a logical product of pixels in the same row and column of the second register group; An image signal editing register including means for detecting overlapping pixel groups. (3) In an image information processing device that edits and processes image information' composed of binary pixels arranged in m rows and n columns, m'
A register group #1 that stores pixels in row n' column, a second register group that stores pixels in m rows and column nA', and the first and second register groups are arranged in row and column directions. means for cyclically shifting, means for generating a logical sum of pixels of the same row and IEJ-crit of the first and second register groups, and storage for the first and second register groups, respectively; 1. A patent edition editing register comprising means for detecting that any pixel having a predetermined logical value contained in image information deviates from the storage area of the first and second register groups.