JPS61148487A - Expander/reducer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an enlargement/reduction device for enlarging or reducing, for example, a binary image.

[Technical background of the invention and its problems] Conventionally, in an image information file device using an optical disk or the like, when storing a read image, displaying the stored image on a display unit, or recording the stored image on a recording device, Image information is enlarged or reduced. In this case, when enlarging or reducing a binary image, for the font that is the constituent unit of each character after enlargement or reduction, the original font used for the calculation is the number that surrounds it, as shown in Figure 9. I got the point. Here, in order to obtain an arbitrary enlargement or reduction ratio, it is necessary to arbitrarily select the analysis font within the range surrounded by the current font, and since it is difficult to process multiple fonts at the same time, it is possible to process only one font at a time. First, there was a drawback that there was a limit to speeding up.

[Object of the Invention] The present invention has been made in view of the above circumstances, and its object is to provide a high-speed and low-cost enlarging/reducing device.

[Summary of the Invention] In order to achieve the above object, the present invention provides an enlargement/reduction device for enlarging and reducing image information 21a, in which data in units of pixels of the image information is stored in storage means for a plurality of rows and columns. Then, the position of the virtual font is calculated according to the stored data for multiple rows and columns, and the position of the new font is calculated according to the position of this virtual font and the scaling ratio, and the data of the original font is calculated. The new font data is output according to the font.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a schematic configuration of an enlargement/reduction device 10 of the present invention used in an image file device, and includes a control circuit 1, a shift register 2.8, a selector 3.6, and a memory 4.
．． 5. It is composed of an arithmetic circuit 7.

As shown in FIG. 2, the size of the original image (character) input from the control unit of the image file device to the enlargement/reduction device 10 is 24×24 pel, and the size of the character after enlargement or reduction is 16×16 pel. , 24x24pe I, 3
2x32pe I, 40x40pel, 48X48pe
The expansion and reduction ratios of these are 3, respectively.
:2.3:3.3:4.3;5.3:6. Therefore, the scaling circuit 10 has a 24x24pe
As shown in FIG. 2, the original image of 1 is divided into blocks of 3x3pe I and processed.

That is, the control circuit 1 controls the entire system. The shift register 2 has image information for each line of each character (as shown in FIGS. 2 and 5) supplied from a control unit of an image file device (not shown) as an external device.
24-bit data for each line) are stored sequentially, and 3
The data is rewritten into parallel data bit by bit and output to the selector 3 and the arithmetic circuit 7. The selector 3 selectively outputs every three bits of data supplied from the shift register 2 to the memory 4.5. The memory 4.5 stores data for each line supplied from the selector 31.
The data for one previous line and the data for one line from the previous time are stored alternately. The selector 6 selectively outputs data for each line supplied from the memory 4.5 to the arithmetic circuit 7.

The arithmetic circuit 7 performs an arithmetic operation using the data supplied from the shift register 2 and the data supplied from the selector 5 (3 bits x 2 columns), and determines the position of the virtual font as shown in FIG. The system calculates the position of the new font as shown in Fig. 4(a) to (8) according to the position of this virtual font and the enlargement/reduction ratio supplied from the overlay control section. For example, if the enlargement/reduction ratio is 3
: In the case of 2, a new font is calculated at the position shown in Figure 4 (a), and when the enlargement/reduction ratio is 3 = 3, a new font is calculated at the position shown in Figure 4 (b), and the enlargement/reduction ratio is 3. The ratio is 3=4
In this case, a new font is calculated at the position shown in (C) in the figure, and when the enlargement/reduction ratio is 3=5, a new font is calculated at the position shown in (1) in the figure ((1), and the enlargement/reduction ratio is In the case of 3:6, a new font is calculated at the position shown in FIG. It outputs the signal strength (a digital signal indicating whether it is a white signal) to the shift register 8 (parallel data of 2 to 6 bits). Data indicating the position of the new font is supplied from the shift register 8 and the arithmetic circuit 7. and data indicating whether the position is a black signal or a white signal are stored for one line, and the data for each line is outputted to the control section as enlarged or reduced data (serial data).

The shift register 2, selector 3, memory 4.5, selector 6, and arithmetic circuit 7 are each connected by a signal line through which 3-bit data is transferred in parallel.

The arithmetic circuit 7 and shift register 8 are connected by a signal line through which 6-bit data is transferred in parallel.

Next, the operation in such a configuration will be explained.

For example, now, image data for each column for one character is sequentially supplied from the control section of the image file device to the shift register 2, and its enlargement/reduction ratio is supplied to the control circuit 1. First, the first column of image data is supplied to the shift register 2. Then, the shift register 2 rewrites the parallel data every 3 bits and outputs it to the selector 3. As a result, the selector 3 selects the memory 4 and sequentially outputs the supplied image data to the memory 4. As a result,
The first column of image data is stored in the memory 4.

Then, the second column of image data is supplied to the shift register 2. Then, the shift register 2 rewrites the parallel data every 3 bits and outputs it to the selector 3 and the arithmetic circuit 7. As a result, the selector 3 selects the memory 5 and sequentially outputs the supplied image data to the memory 5. As a result, the image data of the second column is stored in the memory 5.

At this time, the control circuit 1 outputs a selection signal for the memory 4 to the selector 6. As a result, the selector 6 sequentially outputs the image data of every three bits of the first column supplied from the memory 4 to the arithmetic circuit 7.

Therefore, the arithmetic circuit 7 performs an arithmetic operation using the data supplied from the shift register 2 and the data supplied from the selector 5 (3 bits x 2 columns) to create a virtual font a as shown in FIG. 5 position is calculated, and the position of the new font as shown in FIGS. 4(a) to (e) is calculated according to the position of this virtual font a and the enlargement/reduction ratio supplied from the control section. . For example, if the enlargement/reduction ratio is 3=2, two new fonts at the top of the position shown in Figure 4(a) will be calculated, and if the enlargement/reduction ratio is 3:3, the new fonts will be calculated as shown in Figure 4(b). If the upper six fonts at the position shown are calculated and the enlargement/reduction ratio is 3:4, then the upper eight new fonts at the position shown in the same figure (C) are calculated and the enlargement/reduction ratio is 3:4.
= 5, 15 new fonts at the top of the position shown in Figure (d) are calculated, and when the enlargement/reduction ratio is 326, 18 new fonts at the top of the position shown in Figure (e) are calculated. is calculated.

Further, the arithmetic circuit 7 outputs data indicating the calculated position of the new font and data indicating whether the position is a black signal or a white signal (data corresponding to the original font) to the shift register 8. For example, if the current font is black (white) data, all the corresponding virtual fonts are black (white) data, and whether the new font is black or white is determined by the surrounding virtual fonts. As a result, data indicating the position of the new font supplied from the shift register 8 and the arithmetic circuit 7 and data indicating whether the position is a black signal or a white signal are stored for one line.
Enlarge or reduce data for each line (2 to 6
(bit parallel data) is converted into serial data and output to the control section.

Further, the image data of the third column is supplied to the shift register 2. Then, the shift register 2 rewrites the parallel data every 3 bits and outputs it to the selector 3 and the arithmetic circuit 7. As a result, the selector 3 selects the memory 4 and sequentially outputs the supplied image data to the memory 4. As a result, the image data of the third column is stored in the memory 4.

At this time, the control circuit 1 outputs a selection signal for the memory 5 to the selector 6. As a result, the selector 6 sequentially outputs the image data of every 3 bits of the second column supplied from the memory 5 to the arithmetic circuit 7.

Therefore, the arithmetic circuit 7 performs an arithmetic operation using the data supplied from the shift register 2 and the data supplied from the selector 5 (for two columns of 3 pits), and calculates the position of the virtual font b as shown in FIG. The position of the new font as shown in FIGS. 4(a) to 4(e) is calculated according to the position of this virtual font b and the enlargement/reduction ratio supplied from the control section. For example, if the enlargement/reduction ratio is 3
= 2, the lower two new fonts at the position shown in Figure 4(a) are calculated, and when the enlargement/reduction ratio is 3:3, the lower three new fonts at the position shown in Figure 4(b) are calculated. The font is calculated and
When the enlargement/reduction ratio is 3:4, the lower eight new fonts at the position shown in the same figure (C) are calculated, and the enlargement/reduction ratio is 3=
5, 10 new fonts at the bottom of the position shown in figure (d) are calculated, and if the enlargement/reduction ratio is 320, the figure (
The lower 18 new fonts at the position shown in e) are calculated.

Further, the arithmetic circuit 7 outputs data indicating the calculated position of the new font and data indicating whether the position is a black signal or a white signal (data corresponding to the original font) to the shift register 8. As a result, the shift register 8,
The data indicating the position of the new font supplied from the arithmetic circuit 7 and the data indicating whether the position is a black signal or a white signal are stored for one line, and the data for each line is enlarged or reduced (2 to 2). 6-bit parallel data) is converted into serial data and output to the control section.

Thereafter, the enlargement/reduction process is performed in the same manner as described above for each column of image data.

As mentioned above, since multiple bits of data can be processed simultaneously, the speed can be increased and the configuration can be simplified.

In the above embodiment, the case where the image data is processed for each pixel string of one character as shown in FIG. 5 has been described, but the process is not limited to this. They may be processed simultaneously, or they may be processed for each block (3X31)ei+') within one character, as shown in FIGS. 7 and 8.

[Effects of the Invention] As detailed above, according to the present invention, a high-speed and low-cost enlarging/reducing device can be provided.

[Brief explanation of drawings]

The drawings are for explaining one embodiment of the present invention, and FIG. 1 is a block diagram showing the overall general configuration, FIG. 2 is a diagram showing an example of dividing an original image into blocks, and FIG. 3 is a diagram showing an original font and a virtual font. Figure 4 is a diagram to explain the correspondence between virtual fonts and new fonts. Figure 5 is a diagram to explain the order of processing. FIG. 8 is a diagram for explaining the order of processing in another embodiment, and FIG. 9 is a diagram for explaining conventional enlargement/reduction processing. 1... Control circuit, 2.8... Shift register, 3.
6...Selector, 4.5...Memory, 7...Arithmetic circuit. Applicant's agent Patent attorney Takehiko Suzue Figure 4 3:4 3:5 3
: 5 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Procedural amendment 1. Indication of Case Patent Application No. 59-272206 @ 2. Name of Invention Enlarging/Reducing Device 3. Person Making Amendment Relationship with Case Patent Applicant (307) Toshiba Corporation 4, Agent 1-26 Toranomon, Minato-ku, Tokyo No. 5 No. 17 Mori Building Akira
l1ll Mouth 1, Name of the Invention Enlarging/Reducing Device 2, Claims (1) An enlarging/reducing device for enlarging or reducing binary image information, in which pixel-by-pixel data of the image information is divided into a plurality of rows,
A storage means for storing columns, a specifying means for specifying a scaling ratio, and a position of a virtual dot is calculated according to data for a plurality of rows and columns stored in the storage means, and the position of the virtual dot and the 1. An enlarging/reducing device comprising means for calculating the position of a new dot according to an enlargement/reducing ratio and outputting data of a new dot according to data of an original dot. (2) The scaling device according to claim 1, wherein the scaling ratio is a value expressed as an integer ratio. 3. Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to an enlargement/reduction device for enlarging or reducing, for example, a binary image. [Technical background of the invention and its problems] Conventionally, workstations such as word processors
When storing an image, display the stored image on the display,
When recording with a recording device, image information is enlarged or reduced. In this case, when enlarging or reducing a binary image, for each dot that is the constituent unit of each pattern after enlargement or reduction, the original dot used for the calculation is the number that surrounds it, as shown in Figure 9. I got the point. Here, in order to obtain an arbitrary enlargement or reduction ratio, it is necessary to arbitrarily select a new dot within the range surrounded by the current dot, and since it is difficult to process multiple dots at the same time, it is possible to process only one dot at a time. First, there was a drawback that there was a limit to speeding up. [Object of the Invention] This invention was made in view of the above circumstances, and its object is to provide a high-speed and low-cost enlarging/reducing device. [Summary of the Invention] In order to achieve the above object, the present invention provides an enlargement/reduction device for enlarging and reducing binary image information, in which pixel unit data of the image information is stored in a storage means for a plurality of rows and columns. The position of the virtual dot is calculated according to the stored data for multiple rows and columns, and the position of the new dot is calculated according to the position of the virtual dot and the scaling ratio. New dot data is output according to the data. [Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a schematic configuration of a scaling device 10 of the present invention used in a word processor, and includes a control circuit 1, a shift register 2.8, a selector 3.6, and a memory 4.
．． 5. It is composed of an arithmetic circuit 7. As shown in FIG. 2, the size of the original image (character) input from the control section of the word processor to the enlargement/reduction device 10 is 24 x 24 dots, and the size of the character after enlargement or reduction is 16 x 16 dots, 24 x 24 dots. Dot, 32X3
They are 2 dots, 40x40 dots, and 48x48 dots, and their enlargement and reduction ratios are 3:2.3:
It corresponds to 3.3:4.3; 5.3:6. Therefore, the enlarging/reducing circuit 10 processes a 24.times.24 dot original image by dividing it into blocks of 3.times.3 dots as shown in FIG. That is, the control circuit 1 controls the entire system. The shift register 2 has image information for each line of each character (shown in FIGS. 2 and 5) supplied from a control unit of a word processor (not shown) as an external device.
24-bit data for each line) are stored in 5 sequential order.
The data is rewritten into parallel data every 3 bits and output to the selector 3 and the arithmetic circuit 7. The selector 3 above is
Data of every three bits supplied from the shift register 2 is selectively outputted to the memory 4.5. The memory 4.5 has a memory 1 supplied from the selector 31.
Memory 4. stores data for each line.
5, data for one previous line and data for one line from the previous time are stored alternately. The selector 6 selectively outputs data for each line supplied from the memory 4.5 to the arithmetic circuit 7. The arithmetic circuit 7 performs arithmetic operations using the data supplied from the shift register 2 and the data supplied from the selector 5 (3 bits x 2 columns), and determines the position of the virtual dot as shown in FIG. The position of a new dot as shown in FIGS. 4(a) to (e) is calculated according to the position of this virtual dot and the enlargement/reduction ratio supplied from the control section. . For example, if the enlargement/reduction ratio is 322, a new dot at the position shown in FIG. 4(a) is calculated,
When the enlargement/reduction ratio is 3:3, a new dot is calculated at the position shown in the figure (b), and when the enlargement/reduction ratio is 3=4, a new dot is calculated at the position shown in the figure (C). When the enlargement/reduction ratio is 3=5, a new dot is calculated at the position shown in (d) of the same figure, and when the enlargement/reduction ratio is 3:6, a new dot is calculated at the position shown in (e) of the same figure. is now calculated. Further, the arithmetic circuit 7 outputs data indicating the calculated position of the new dot and data indicating whether the position is a black signal or a white signal (2 to 6 bit parallel data) to the shift register 8. be. The data indicating the position of the new dot supplied from the shift register 8 and the arithmetic circuit 7 and the data indicating whether the position is a black signal or a white signal are stored for one line, and the data for each line is expanded or This is output to the control section as reduced data (serial data). The shift register 2, selector 3, memory 4.5, selector 6, and arithmetic circuit 7 are each connected by a signal line through which 3-bit data is transferred in parallel. The arithmetic circuit 7 and shift register 8 are connected by a signal line through which 6-bit data is transferred in parallel. Next, the operation in such a configuration will be explained. For example, now, image data for each column for one character pattern is sequentially supplied from the control section of the word processor to the shift register 2, and its enlargement/reduction ratio is supplied to the control circuit 1. First, the first column of image data is supplied to the shift register 2. Then, the shift register 2 rewrites the parallel data every 3 bits and outputs it to the selector 3. As a result, the selector 3 selects the memory 4 and sequentially outputs the supplied image data to the memory 4. As a result, the first column of image data is stored in the memory 4. Then, the second column of image data is supplied to the shift register 2. Then, the shift register 2 rewrites the parallel data every 3 bits and outputs it to the selector 3 and the arithmetic circuit 7. As a result, the selector 3 selects the memory 5 and sequentially outputs the supplied image data to the memory 5. As a result, the image data of the second column is stored in the memory 5. At this time, the control circuit 1 outputs a selection signal for the memory 4 to the selector 6. Thereby, the selector 6 sequentially outputs the image data for every three pits in the first column supplied from the memory 4 to the arithmetic circuit 7. Therefore, the arithmetic circuit 7 performs arithmetic operations using the data supplied from the shift register 2 and the data supplied from the selector 5 (for two columns of 3 pits), and determines the position of the virtual dot a as shown in FIG. The position of a new dot as shown in FIGS. 4(a) to 4(e) is calculated according to the position of this virtual dot a and the enlargement/reduction ratio supplied from the control section. For example, if the enlargement/reduction ratio is 3=2, two new dots at the top of the position shown in FIG.
If 6 new dots at the top of the position shown in (C) are calculated and the enlargement/reduction ratio is 3=4, then 8 new dots at the upper part of the position shown in the same figure (C) are calculated and the enlargement/reduction ratio is 3. If =5,
15 new dots are calculated at the upper part of the position shown in FIG. 2(d), and when the enlargement/reduction ratio is 326, 18 new dots are calculated at the upper part of the position shown in FIG. 2(e). Further, the arithmetic circuit 7 transfers data indicating the calculated position of the new dot and data indicating whether the position is a black signal or a white signal (data corresponding to the original dot) to a shift register 8.
Output to. For example, if the current dot is black (white) data, all the corresponding virtual dots are black (white) data, and whether a new dot is black or white is determined by the surrounding virtual dots. As a result, data indicating the position of a new dot supplied from the shift register 8 and the arithmetic circuit 7 and data indicating whether the position is a black signal or a white signal are stored for one line, and the data for each line is stored. The enlarged or reduced data (2 to 6 bit parallel data) is converted into serial data and output to the control section. Further, the image data of the third column is supplied to the shift register 2. Then, the shift register 2 rewrites the parallel data every 3 bits and outputs it to the selector 3 and the arithmetic circuit 7. As a result, the selector 3 selects the memory 4 and sequentially outputs the supplied image data to the memory 4. As a result, the image data of the third column is stored in the memory 4. At this time, the control circuit 1 outputs a selection signal for the memory 5 to the selector 6. As a result, the selector 6 sequentially outputs the image data of every 3 bits of the second column supplied from the memory 5 to the arithmetic circuit 7. Therefore, the arithmetic circuit 7 performs arithmetic operations using the data supplied from the shift register 2 and the data supplied from the selector 5 (for two columns of 3 pits), and determines the position of the virtual dot b as shown in FIG. According to the position of this virtual dot b and the enlargement/reduction ratio supplied from the control section, the position of a new dot as shown in FIGS. 4(a) to 4(e) is calculated. For example, if the enlargement/reduction ratio is 3:2, two new dots at the bottom of the position shown in Fig. 4(a) are calculated, and if the enlargement/reduction ratio is 3:3, the new dots are calculated in the position shown in Fig. 4(b). If three new dots at the bottom of the position shown are calculated and the enlargement/reduction ratio is 3=4, then eight new dots at the bottom of the position shown in the same figure (C) are calculated and the enlargement/reduction ratio is 3: 5, W
Ten new dots at the lower part of the fI diagram (d) are calculated, and when the enlargement/reduction ratio is 3=6, 18 new dots at the lower part of the position shown in the figure (1B>) are calculated. Further, the arithmetic circuit 7 transfers data indicating the calculated position of the new dot and data indicating whether the position is a black signal or a white signal (data corresponding to the original dot) to a shift register 8.
Output to. As a result, data indicating the position of a new dot supplied from the shift register 8 and the arithmetic circuit 7 and data indicating whether the position is a black signal or a white signal are stored for one line, and the data for each line is stored. The enlarged or reduced data (2 to 6 bit parallel data) is converted into serial data and output to the control section. Thereafter, the enlargement/reduction process is performed in the same manner as described above for each column of image data. As mentioned above, since data from multiple pits can be processed simultaneously, the speed can be increased and the configuration can be simplified. In the above embodiment, the case where the image data is processed for each pixel string of one character pattern as shown in FIG. It is also possible to process the characters simultaneously, or to process each block (3×3 dots) within one character as shown in FIGS. 7 and 8. Further, it is sufficient if the magnification is expressed as an integer ratio. Furthermore, although the character pattern has been described, the invention is not limited to this, and as long as the magnification is specified, the image may be enlarged or reduced within a predetermined range (all or part). [Effects of the Invention] As detailed above, according to the present invention, a high-speed and low-cost enlarging/reducing device can be provided. 4. Brief description of the drawings The drawings are for explaining one embodiment of the present invention. Fig. 1 is a block diagram showing the overall general configuration, Fig. 2 is a diagram showing an example of dividing the original image into blocks, and Fig. 3 The figure is a diagram to explain the correspondence between original dots and virtual dots, Figure 4 is a diagram to explain the correspondence between virtual dots and new dots, and Figure 5 is a diagram to explain the order of processing. 6 to 8 are diagrams for explaining the order of processing for other embodiments, and FIG. 9 is a diagram for explaining conventional enlargement/reduction processing. 1... Control circuit, 2.8... Shift register, 3.
6...Selector, 4.5...Memory, 7...Arithmetic circuit. Applicant's representative Patent attorney Takehiko Suzue Figure 4 (C) 3:4 3:5 3:6 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9

Claims (2)

[Claims] (1) In an enlargement/reduction device that enlarges or reduces binary image information, data in units of pixels of the image information is divided into a plurality of rows,
A storage means for storing columns, a specifying means for specifying a scaling ratio, and a position of a virtual font is calculated according to the data for a plurality of rows and columns stored in the storage means, and the position of the virtual font and the 1. A scaling device comprising means for calculating the position of a new font according to a scaling ratio and outputting data of a new font according to data of an original font. (2) The scaling device according to claim 1, wherein the scaling ratio is a value expressed as an integer ratio.