JPS58115521A - Bus controlling system - Google Patents

Abstract

PURPOSE:To prevent the malfunction of the system due to the function fault or the like of a channel device, by providing a circuit, which inhibits other devices from using a bus during the memory access time of a device to which a bus use permission signal is given, in a bus controlling part. CONSTITUTION:When channel CH devices 5a-5z output direct memory access DMA request signals DMARQ to a bus controlling part 2 through a common bus 4, the controlling part 2 inputs these signals to a priority level encoder and selects a signal having a preliminarily set highest priority level from signals DMARQ and outputs this signal to a decoder. The decoder outputs level 1 to only the FF which outputs a permission signal DMAA0 corresponding to this selected signal number. A bus controlling right is given to the CH device to which the signal DMAA0 is given, and an address signal, a read/write signal, a strobe signal, etc. to a memory 3 are outputted to the bus 4 to access the memory 3. The controlling part 2 transmits the signal DMAA0 continuously during the memory access time of the CH device to inhibit other CH devices from using the bus by an NAND gate.

Description

DETAILED DESCRIPTION OF THE INVENTION 0 Technical Field of the Invention The present invention relates to a bus control system, and particularly to a bus control system in which one device among a plurality of input/output devices connected to a common bus accesses memory without going through a processing device. Regarding control method.

Background of O technology A processing device (hereinafter referred to as CPU) via a common path.

A direct memory access (hereinafter referred to as DMA) function is used in which a plurality of input/output control devices and memories transmit and receive data, and the input/output control device directly accesses the memory. For this reason, a path control unit is provided that controls the timing of use of a common path for DM users by an input/output control device (hereinafter referred to as a channel device).

O Prior Art and Problems FIG. 1 is a block diagram showing the general configuration of a data processing system having the above-mentioned DMA function.

In the figure, l is the CPU, 2-digit bus controller, 3#i
Memory, 4 is a common path, and e5a to 5z are channel devices.

6a to 6zt= are input/output devices. In the system shown in the figure, path controller 2 fi-CPU 1
The bus control function is added to the CPU 1 as part of the CPU 1, but the bus controller 2
may be provided. Input/output devices 6a to 6ztj:
For example, there are printers, card readers, and display devices, each of which transmits data through channel devices 53 to 5ze.

Figure 2 shows input/output devices 63 to 63 based on the conventional bus control method.
Is one device in 6z DMA? if you do it.

It is a time chart of signals and data exchanged between each device. In the figure, CLK is the reference clock, and MAA
is the bus mastership permission signal, DMARQ is the MA request signal, and R/W is the read/write mode signal.

Tatami D8Vi Fi Mistrobe No., Btsy is bus busy signal, +8RVo#'i response signal. Below @1
1) MA operation in the conventional system will be explained using FIGS.

Among the input/output devices 68 to 6z, l) the device making the MAi request outputs a DMA internal request signal (not shown) to each channel device 5a to 5z. The channel device that receives the DMA internal request No. 1g outputs the request signal +DMA1'LQ = i level "0" to the node in synchronization with the reference clock CI, K.
Is it possible to select the crotch in advance from among each channel device that outputs ordinary Q? A permission signal fD for the channel device 5a of the printer 6a, for example, a device 1 with a high priority (priority).
The MAAt-level is set to "0'" and control of the common bus 4 is given.

When the channel device 5 a tri +DMAA reaches the "0'" level, a timing for accessing the memory 3 is generated and a DMA operation is started. That is, DMA timing is generated by two flip-flops FFI and FF2. First, 4) FF1i is set (output level "1"') at the timing of the next reference clock CLK when DMAA becomes "O" level, and further, the output of FF2 is set at the next clock by the "1 level" output of FFI.

The channel device 5a outputs the outputs of this FFI and FF2. The bus controller 2 prohibits other channel devices from using the bus during the morning when the high BUOY signal is at the "θ" level. Furthermore, channel device 5 a d eFFI
and FF2 output) Strobe signal *D
8vit-output. At this time, if the R/W signal specifies the read mode, the memory 3 will receive the strobe signal D8V.
Data DT1 stored at address AD19-- specified at the first CLK timing after i becomes "01"
51i path 4 and a response signal 4) 8R
VOk "O""" level.

The response signal AO8FLVo output from the memory 3 causes the channel device 5a to switch to FFI? Reset. By resetting FF1, the output of FF2 is also reset (to "0m level") at the 9th CLK timing.According to the output conditions of FFI and FF2 described above, the channel device 5a outputs the strobe signal bone D8Vi. s Memory address AD19-#, R/W, and BU8Y are reset in sequence. With the above operation, the DMA sequence is completed. As mentioned above, in the conventional bus control system, 1) M.A.
It is necessary to generate all memory access timing within the channel device, which has the drawback of complicating the circuitry of each channel device. Furthermore, in the conventional method, DM
Bus busy signal output by channel device in A + BUS
Y prohibits the bus controller 2 from outputting the path mastership permission signal 4) DMAA to other channel devices. Therefore, abnormal output of the BU8Y signal due to a malfunction of the channel device during DMA, etc., causes abnormal operations such as granting or prohibiting the bus control right by the bus controller 2, which results in system malfunction 9 and functional outage. It also had a drawback.

〇　Purpose of the invention The object of the present invention is to obviate the above-mentioned drawbacks of the prior art.

This not only simplifies the circuit configuration of each channel device.

It is an object of the present invention to provide a path control method that eliminates the risk of system malfunctions and system outages due to functional failures of channel devices during DMA, and can perform DMA with higher reliability.

0 Structure of the invention To achieve the above object, the present invention provides a bus control system.

A processing unit, a bus control unit, a plurality of input/output devices, and a memory are each connected to a common bus, and the bus control unit gives a bus mastership permission signal to one of the plurality of input/output devices.
In a bus control method in which one device accesses memory without going through the processing unit w, the bus control unit includes a sending circuit that continues to send out a core permission signal during the memory access period of the device in which the permission signal is fully increased, and other inputs. A circuit for controlling exclusion according to the presence/absence of the access lr permission signal of the output device is provided;
It is characterized in that other devices are prohibited from using the bus during the memory access period of the device that has given the permission signal.

0 Embodiment of the Invention FIG. 3 is a time chart of signals or data transmitted and received between devices during DMA operation in the path control system of the present invention. FIGS. 4 and 5 are block diagrams showing an embodiment of a channel device and a path controller in the bus control system of the present invention. In Figure 4, IC4A, 4B#i bus driver.

In FIG. 5, 7#i is a priority enhancer and 8 is a decoder.

That is, as shown in FIG.
The AA also specifies the memory access permission period of the channel device.

As a result, the DMA address A output by the channel device
I) 19-1 and mode signal R/W key 1) MAA is kept at an effective level only during the period when it is at the effective level (“θ” level. Below, based on Fig. 3, it is shown in Fig. 4.5. The operation of the embodiment will be explained.The system configuration uses the block diagram shown in FIG. 1 as is.

Input/output devices #68 to 6z of each channel device 5a to 5zu
request signal +nMA by DMA internal request f1 from
Output l'tQ. In the embodiment of the channel device shown in FIG. 4, when the DMA internal request signal goes to level "1", the F
F4 #'i Inverts the Q output from level "1" to "θ"' in synchronization with the fall of the reference clock pulse. This Q output (tl) is outputted to the path controller 2 via the bus 4 as DMARQ. The request signal +DMARQoS-fDMARQn output from each channel device 5a to 5z of the bus controller 2#i shown in FIG. 5 is input to the priority encoder 7. The encoder 7 is at the "0'" level. 11) The request signal 9 is set to the priority level set in advance in the MA-Q, and the signal number 9 is selected. ” is output to the decoder 8. The decoder 8 outputs the level "1" only to the FF 5 which outputs the permission signal DMAA (1) DMAAo in this case) corresponding to the signal number selected by the encoder 7. As a result, the encoder 7 outputs level "1". The Q output i level of only one FF5 becomes "0", and the request signal fD
The grant signal corresponding to the channel device with the highest priority among the channel devices that output MARQf (in this case, Tatami D'
1llllAAO) becomes the "0" level and is given bus mastership.

The channel device that has been given bus mastery switches to the inverter IC2C when IDMAA goes to the level "θ'".
The Q output of FF'4 is reset via the request signal D
MARQTh level " at the next clock CLK timing"
Return to 1″″. In addition, the IGOA level power of the DMAA is connected to the bus driver IC4 via the inverter IC2At.
This becomes a drive signal for B and IC4C. When the level "1'" is applied to the drive signal, the path driver ICs 4B and 4C output a signal level previously applied to the input terminal onto the path 4. As a result, memory address AI)1
Each signal level of 9-# and mode signal R/W will be output onto bus 4. Furthermore, inverter IC2At
The output signal becomes a drive signal for the path driver IC4A via the AND gate ICIB and ll'F3. With this drive signal, the strobe signal -DSVi is activated at the next CLK timing after the AD19-#, R/W signal is output.
Ka effective level (“04 level”) and null.

When the strobe signal DSVi reaches the "O" level.

Memory 3 is a mode signal R/W (read mode in this case)
Therefore, the data stored at the address given by ADZ9-1 (DT15-#') is output onto path 4.

At the same time, the response signal 5RVo is set to level "0".

When the level of the blue 5RVo becomes "θ'", the channel device reads the data 1) T15-# output from the memory 3, and also inverts the inverter IC2B and the AND gate ■cI.
The Q output of FF3 is reset through B, and the strobe signal +D8Vi'r level is reset to "1" by connecting it with the output of the path driver I (?4A).

With the rise of this strobe signal *D8Vi, the memory 3 changes the response signal - to 8R+Vo and the data D'l"15.
-Reset a.

The path controller 2 uses the AND gate ICICK to input the rechannel device's step signal D8Vi and the memo 173.
According to the AND condition of the output level of the response signal 4ISRVo from %DMAA (in this case, 4DMAAo)k, the level is reset to ``1'' and the end of the bus sequence is instructed. That is, by inverting the level of %DMAA to ``1'''', .

The channel device sets the drive signal to the bus driver IC4B and IC4C via the inverter IC2At to level “0”.
The address is AD19-1. Reset mode signal R/W. Here, during a period when one channel device has the right to control the bus, prohibition of other channel devices from using the bus is performed by the Nantes Gate IC 3, as shown in FIG. As mentioned above, since the bus support period lvlwo is also specified by the permission signal DMAAK of the path controller 2, the IC3 outputs 41 DMAAo~+DMAA.
NAND of n? Depending on the action K, the decoding operation of the decoder 8 is prohibited or permitted.

As described in detail above, in this embodiment, the path control permission signal bone 1) The bus busy signal I which the channel device given MAA outputs from its own timing generation circuit.
BUSY is not required. Arrived DMA address AI) 1
9-1 and mode signal R/W There is no need for timing generation means (FFI and FF2) for all sets/resets, and the circuit configuration on the channel device side can be greatly simplified. Furthermore, the bus control period can also be specified using the path controller 2's Tatami I) MAA.
As a result, the reliability of the entire system can be improved.

0 DETAILED DESCRIPTION OF THE INVENTION As described above, according to the present invention, the circuit configuration of the channel device provided in each input/output device can be greatly simplified, making it possible to provide a low-cost channel device. Furthermore, the bus control unit (path controller) can now specify the path control permission period for each channel device, which greatly eliminates the risk of system malfunctions and outages due to functional failures of channel devices that perform DMA. is,
It is possible to provide a bus control method that has excellent effects such as improving the reliability of the system.

[Brief explanation of drawings]

Figure 1 is a block diagram showing the general configuration of a data processing system, and Figure I@2 is a DMA diagram in the conventional bus control system.
Figure 3 is a time chart showing the bus 7-sequence during DMA in the bus control method of the present invention, Figures 4 and 5 are an implementation of the channel device and path controller in the present invention, respectively. FIG. 2 is a block diagram illustrating an example. 2 is the no(s) controller. 3IIi memory, 5a to 5z are channel devices e6a to 6
z is an input/output device. 1st what

Claims (1)

[Claims] A processing device, a bus control unit, a plurality of input/output control devices, and a memory are each connected to a common path, and one device among the plurality of input/output control devices to which the path control unit has given a bus support permission signal. In a bus control method in which a memory is accessed without going through the processing device, the path control unit is provided with the permission signal and continues to send out the core permission signal during the memory access period of the memory, and other input/output control. A bus control system comprising: a circuit for performing exclusion control depending on the presence/absence of an access tm permission signal of a device, and prohibiting other devices from using a bus during a memory access period of the device to which the # permission signal has been given.