JPS5769457A - Microprogram controller - Google Patents

Microprogram controller

Info

Publication number
JPS5769457A
JPS5769457A JP14588780A JP14588780A JPS5769457A JP S5769457 A JPS5769457 A JP S5769457A JP 14588780 A JP14588780 A JP 14588780A JP 14588780 A JP14588780 A JP 14588780A JP S5769457 A JPS5769457 A JP S5769457A
Authority
JP
Japan
Prior art keywords
instruction
executed
branching
selects
information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14588780A
Other languages
Japanese (ja)
Inventor
Yasuo Wakamiya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14588780A priority Critical patent/JPS5769457A/en
Publication of JPS5769457A publication Critical patent/JPS5769457A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/28—Enhancement of operational speed, e.g. by using several microcontrol devices operating in parallel

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)

Abstract

PURPOSE:To shorten the time of instruction execution by prereading instructions coming next when a branching is executed or not simultaneously, if an instruction being executed is conditional branch one when the next instruction is to be prefetched in an instruction execution cycle. CONSTITUTION:A fetch control circuit 11 in an instruction fetch part 1 discriminate whether an instruction is branch one or not and, when it is the former case, sends pieces of information when branching is executed and not to instruction-prefetching address counters 12 and 13 are connected to an address selecting circuit 14, which is selects one of two address counters on the basis of information, on whether the branching is executed or not, sent through a fetch control circuit 11 from an instruction execution part 3 to access a memory part 2 for the next prefetching operation. An instruction word selecting circuit 17 also selects an instruction to be executed next and supplies it to an executed-instruction register 18.
JP14588780A 1980-10-17 1980-10-17 Microprogram controller Pending JPS5769457A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14588780A JPS5769457A (en) 1980-10-17 1980-10-17 Microprogram controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14588780A JPS5769457A (en) 1980-10-17 1980-10-17 Microprogram controller

Publications (1)

Publication Number Publication Date
JPS5769457A true JPS5769457A (en) 1982-04-28

Family

ID=15395341

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14588780A Pending JPS5769457A (en) 1980-10-17 1980-10-17 Microprogram controller

Country Status (1)

Country Link
JP (1) JPS5769457A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6282402A (en) * 1985-10-07 1987-04-15 Toshiba Corp Sequence controller
JPH0235525A (en) * 1988-07-25 1990-02-06 Fujitsu Ltd Instruction fetch control method
JPH04117526A (en) * 1990-09-07 1992-04-17 Koufu Nippon Denki Kk Microprogram controller
JPH06250843A (en) * 1993-02-26 1994-09-09 Agency Of Ind Science & Technol Arithmetic processing method and arithmetic unit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6282402A (en) * 1985-10-07 1987-04-15 Toshiba Corp Sequence controller
JPH0235525A (en) * 1988-07-25 1990-02-06 Fujitsu Ltd Instruction fetch control method
JPH04117526A (en) * 1990-09-07 1992-04-17 Koufu Nippon Denki Kk Microprogram controller
JPH06250843A (en) * 1993-02-26 1994-09-09 Agency Of Ind Science & Technol Arithmetic processing method and arithmetic unit

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