JPS5765946A - Mfm demodulating circuit - Google Patents

Mfm demodulating circuit

Info

Publication number
JPS5765946A
JPS5765946A JP55142110A JP14211080A JPS5765946A JP S5765946 A JPS5765946 A JP S5765946A JP 55142110 A JP55142110 A JP 55142110A JP 14211080 A JP14211080 A JP 14211080A JP S5765946 A JPS5765946 A JP S5765946A
Authority
JP
Japan
Prior art keywords
mfm
signal
clock
shift register
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55142110A
Other languages
Japanese (ja)
Inventor
Keizo Nishimura
Hiroyuki Kimura
Yasunori Kanazawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP55142110A priority Critical patent/JPS5765946A/en
Priority to DE3140431A priority patent/DE3140431C2/en
Priority to US06/311,023 priority patent/US4472686A/en
Publication of JPS5765946A publication Critical patent/JPS5765946A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4904—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using self-synchronising codes, e.g. split-phase codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
    • H04L7/0066—Detection of the synchronisation error by features other than the received signal transition detection of error based on transmission code rule
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/042—Detectors therefor, e.g. correlators, state machines

Abstract

PURPOSE:To obtain a stable nonadjusting MFM demodulating circuit, by using an element stable against temperature such as a shift register for demodulation. CONSTITUTION:An MFM signal (a) is inputted to a four-stage shift register 10 which is operated by a clock signal (b) of the half of the MFM signal pulse period, and MFM signals (c)-(f) shifted by every half period are obtained as outputs. Signals (e) and (f) are inputted to an exclusive OR circuit 16, and a signal (k) where a demodulated signal is included in every half of the MFM signal period is outputted to an output (h), and this signal (k) is taken in a flip-flop 17 by a demodulation clock (i). The demodulation clock (i) is obtained by reducing the output of a clock generator 3 to the half by a frequency divider 14, and its phase id cor rected on a basis of a coincidence output (g) of a coincidence detecting circuit 11 which detectes whether outputs (c)-(f) of the four-stage shift register 10 coinside with a specific pattern of all ''1'' or not.
JP55142110A 1980-10-13 1980-10-13 Mfm demodulating circuit Pending JPS5765946A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP55142110A JPS5765946A (en) 1980-10-13 1980-10-13 Mfm demodulating circuit
DE3140431A DE3140431C2 (en) 1980-10-13 1981-10-12 Demodulator circuit for demodulating a modulated digital signal
US06/311,023 US4472686A (en) 1980-10-13 1981-10-13 Circuit for reproducing and demodulating modulated digital signals

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55142110A JPS5765946A (en) 1980-10-13 1980-10-13 Mfm demodulating circuit

Publications (1)

Publication Number Publication Date
JPS5765946A true JPS5765946A (en) 1982-04-21

Family

ID=15307647

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55142110A Pending JPS5765946A (en) 1980-10-13 1980-10-13 Mfm demodulating circuit

Country Status (1)

Country Link
JP (1) JPS5765946A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61159841A (en) * 1985-01-08 1986-07-19 Sanyo Electric Co Ltd Clock synchronizing system

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49114308A (en) * 1973-02-12 1974-10-31
JPS503563A (en) * 1973-05-12 1975-01-14
JPS528765A (en) * 1975-07-09 1977-01-22 Sony Corp Dm-nrz signal conversion method
JPS5528567A (en) * 1978-08-18 1980-02-29 Sanyo Electric Co Ltd Mfm demodulator circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49114308A (en) * 1973-02-12 1974-10-31
JPS503563A (en) * 1973-05-12 1975-01-14
JPS528765A (en) * 1975-07-09 1977-01-22 Sony Corp Dm-nrz signal conversion method
JPS5528567A (en) * 1978-08-18 1980-02-29 Sanyo Electric Co Ltd Mfm demodulator circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61159841A (en) * 1985-01-08 1986-07-19 Sanyo Electric Co Ltd Clock synchronizing system
JPH0344702B2 (en) * 1985-01-08 1991-07-08 Sanyo Electric Co

Similar Documents

Publication Publication Date Title
EP0187504A3 (en) Digital phase correlator
JPS5377131A (en) Solid state pick up unit
JPS5765946A (en) Mfm demodulating circuit
JPS5757051A (en) Fm stereo receiver
JPS52114254A (en) Demodulation unit
EP0197708A3 (en) Digital zero if circuit
JPS5765945A (en) Demodulating circuit
JPS648821A (en) Differential relay
JPS5680944A (en) Synchronism detecting circuit of digital receiver
JPS5614727A (en) Phase comparator of digital pll circuit
JPS5666947A (en) Data transmission method
JPS5621440A (en) Stuff synchronizing system
JPS566568A (en) Sampling method for facsimile signal
EP0274841A3 (en) Processing quadrature signals
JPS5513409A (en) Digital differential analyzer
JPS6484948A (en) Demodulation system for frequency modulation signal
JPS5717236A (en) Detector for synchronism
JPS5399860A (en) Phase shifter
JPS5687211A (en) Digital demodulating circuit
JPS537165A (en) Synchronism detecting circuit of phase control circuit
JPS57211565A (en) Selecting circuit for signal
JPS5570922A (en) Demodulation system of digital signal
JPS54100243A (en) Redundant multi-phase clock generator circuit
JPS52131443A (en) Phase synchronization circuit
JPS5635551A (en) Digital phase detecting system