JPS5758321A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5758321A
JPS5758321A JP13262780A JP13262780A JPS5758321A JP S5758321 A JPS5758321 A JP S5758321A JP 13262780 A JP13262780 A JP 13262780A JP 13262780 A JP13262780 A JP 13262780A JP S5758321 A JPS5758321 A JP S5758321A
Authority
JP
Japan
Prior art keywords
film
protruded
substrate
etched
plasma etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13262780A
Other languages
Japanese (ja)
Inventor
Shigeru Morita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP13262780A priority Critical patent/JPS5758321A/en
Publication of JPS5758321A publication Critical patent/JPS5758321A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To avoid occurrence of cutting of Al wiring in subsequent processes, by removing the protruded part of an Si nitride film yielded in providing a hole in etching of a multi-layered film, by plasma etching. CONSTITUTION:An Si oxide film 22 and the Si nitride film 23 are formed on an Si substrate 21, and a double layered film is constituted. A resist mask 24 is formed on said double layered film. Thereafter film 23 is etched by plasma etching. Then the film 22 is etched with the thickness of several hundred Angstrom being remained. The film 22 is overetched, and the film 23 is protruded in a eaves shape and exposed. Then, the plasma etching is performed again on the protruded film 23, and the eaves shaped protruded part 23a is removed. Then, by heating the substrate 21, a resist 25 which is protruded in an eaves shape is flowed. Said flowed resist 25 and the film 22 are closely contacted. Thereafter, the film 22 remained on the substrate 21 is completely etched, and the surface of the substrate 21 is exposed.
JP13262780A 1980-09-24 1980-09-24 Manufacture of semiconductor device Pending JPS5758321A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13262780A JPS5758321A (en) 1980-09-24 1980-09-24 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13262780A JPS5758321A (en) 1980-09-24 1980-09-24 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5758321A true JPS5758321A (en) 1982-04-08

Family

ID=15085738

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13262780A Pending JPS5758321A (en) 1980-09-24 1980-09-24 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5758321A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5057186A (en) * 1989-07-28 1991-10-15 At&T Bell Laboratories Method of taper-etching with photoresist adhesion layer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5057186A (en) * 1989-07-28 1991-10-15 At&T Bell Laboratories Method of taper-etching with photoresist adhesion layer

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