JPS5755451A - Information processor - Google Patents

Information processor

Info

Publication number
JPS5755451A
JPS5755451A JP12921280A JP12921280A JPS5755451A JP S5755451 A JPS5755451 A JP S5755451A JP 12921280 A JP12921280 A JP 12921280A JP 12921280 A JP12921280 A JP 12921280A JP S5755451 A JPS5755451 A JP S5755451A
Authority
JP
Japan
Prior art keywords
operand
instruction
address
executed
storage device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12921280A
Other languages
Japanese (ja)
Inventor
Hirokimi Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP12921280A priority Critical patent/JPS5755451A/en
Publication of JPS5755451A publication Critical patent/JPS5755451A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30058—Conditional branch instructions

Abstract

PURPOSE:To achieve system constitution with flexibility, by detecting that the operand section of an instruction word read out from a storage device is an even or odd number and designating the address mode. CONSTITUTION:The instruction word system is used, which is set with the number of bits being a multiple of an even number for number of bits constituting the content in minumum unit for the address of a main storage device 5. The instruction word read out from the main storage device 5 is applied to an instruction word register 3, and the instruction is executed by decoding the operation section and the operand section. As a result of the operation section, if it is a jump instruction, a control circuit 2 detects if the operand is an even number, and if it is an even number, the content of the operand is applied to a program counter 1 and the jump instruction is executed with a normal address mode. On the other hand, if an odd number, the address designated at the operand is defined as n, and the content at the address (n-1) is read out and the jump instruction is executed with the indirect address mode.
JP12921280A 1980-09-19 1980-09-19 Information processor Pending JPS5755451A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12921280A JPS5755451A (en) 1980-09-19 1980-09-19 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12921280A JPS5755451A (en) 1980-09-19 1980-09-19 Information processor

Publications (1)

Publication Number Publication Date
JPS5755451A true JPS5755451A (en) 1982-04-02

Family

ID=15003900

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12921280A Pending JPS5755451A (en) 1980-09-19 1980-09-19 Information processor

Country Status (1)

Country Link
JP (1) JPS5755451A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0136699A2 (en) * 1983-10-06 1985-04-10 Hitachi, Ltd. Programmable controller

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50100940A (en) * 1973-12-31 1975-08-11
JPS5414650A (en) * 1977-07-06 1979-02-03 Hitachi Ltd Data processor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50100940A (en) * 1973-12-31 1975-08-11
JPS5414650A (en) * 1977-07-06 1979-02-03 Hitachi Ltd Data processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0136699A2 (en) * 1983-10-06 1985-04-10 Hitachi, Ltd. Programmable controller

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