JPS57208686A - Semiconductor storage device - Google Patents

Semiconductor storage device

Info

Publication number
JPS57208686A
JPS57208686A JP56092455A JP9245581A JPS57208686A JP S57208686 A JPS57208686 A JP S57208686A JP 56092455 A JP56092455 A JP 56092455A JP 9245581 A JP9245581 A JP 9245581A JP S57208686 A JPS57208686 A JP S57208686A
Authority
JP
Japan
Prior art keywords
supplied
circuit
bus
line
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56092455A
Other languages
Japanese (ja)
Inventor
Masao Taguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56092455A priority Critical patent/JPS57208686A/en
Publication of JPS57208686A publication Critical patent/JPS57208686A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Landscapes

  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To increase the reading speed in the page mode, by reading asynchronously the data signals on a common data bus line by means of the residul bits of a row address. CONSTITUTION:In the reading mode, the -RAS is changed to an active state from an inactive state. A line address is fetched to a buffer circuit 5, and the address bits within a part 5a are supplied to a word line driving circuit 2 via a line decoder 3. At the same time, the address bits within a part 5b are supplied to the circuit 2 via a word line driving clock generating circuit 4. Thus a line wire in a memory cell array 1 is driven, and the holding information of each cell is transferred onto the bit wire. Then the state of the -CAS is inverted, and the output of a row decoder 7 selects a sense amplifier 6. Then the data is delivered onto a bus 8. Meanwhile the bit signal and its complement signal supplied from the part 5b are supplied to a bus selecting circuit 9, and the bit signal on the bus 8 is applied to an output buffer 10.
JP56092455A 1981-06-16 1981-06-16 Semiconductor storage device Pending JPS57208686A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56092455A JPS57208686A (en) 1981-06-16 1981-06-16 Semiconductor storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56092455A JPS57208686A (en) 1981-06-16 1981-06-16 Semiconductor storage device

Publications (1)

Publication Number Publication Date
JPS57208686A true JPS57208686A (en) 1982-12-21

Family

ID=14054855

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56092455A Pending JPS57208686A (en) 1981-06-16 1981-06-16 Semiconductor storage device

Country Status (1)

Country Link
JP (1) JPS57208686A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62250589A (en) * 1986-04-23 1987-10-31 Hitachi Vlsi Eng Corp Semiconductor integrated circuit device
JPS63501045A (en) * 1985-09-23 1988-04-14 エヌシーアール インターナショナル インコーポレイテッド Memory device capable of page mode operation and page mode operation method of memory system
EP0307945A2 (en) * 1987-09-17 1989-03-22 Wang Laboratories Inc. Memory control apparatus for use in a data processing system
JPH02177192A (en) * 1988-12-22 1990-07-10 Richard C Foss Large capacity dynamic type semiconductor memory
JP2005149590A (en) * 2003-11-13 2005-06-09 Nec Electronics Corp Semiconductor memory and its control method

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63501045A (en) * 1985-09-23 1988-04-14 エヌシーアール インターナショナル インコーポレイテッド Memory device capable of page mode operation and page mode operation method of memory system
JPS62250589A (en) * 1986-04-23 1987-10-31 Hitachi Vlsi Eng Corp Semiconductor integrated circuit device
EP0307945A2 (en) * 1987-09-17 1989-03-22 Wang Laboratories Inc. Memory control apparatus for use in a data processing system
JPH02177192A (en) * 1988-12-22 1990-07-10 Richard C Foss Large capacity dynamic type semiconductor memory
JP2005149590A (en) * 2003-11-13 2005-06-09 Nec Electronics Corp Semiconductor memory and its control method
JP4614650B2 (en) * 2003-11-13 2011-01-19 ルネサスエレクトロニクス株式会社 Semiconductor memory device

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