JPS57200997A - Non-volatile semiconductor memory - Google Patents

Non-volatile semiconductor memory

Info

Publication number
JPS57200997A
JPS57200997A JP8546681A JP8546681A JPS57200997A JP S57200997 A JPS57200997 A JP S57200997A JP 8546681 A JP8546681 A JP 8546681A JP 8546681 A JP8546681 A JP 8546681A JP S57200997 A JPS57200997 A JP S57200997A
Authority
JP
Japan
Prior art keywords
boosting
writing
wires
circuit
writing circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8546681A
Other languages
Japanese (ja)
Inventor
Hiroshi Iwahashi
Masamichi Asano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP8546681A priority Critical patent/JPS57200997A/en
Priority to GB8205687A priority patent/GB2094086B/en
Priority to US06/353,515 priority patent/US4506350A/en
Priority to DE3207485A priority patent/DE3207485C2/en
Priority to DE3249671A priority patent/DE3249671C2/de
Publication of JPS57200997A publication Critical patent/JPS57200997A/en
Priority to US06/630,863 priority patent/US4597062A/en
Priority to GB08420735A priority patent/GB2144006B/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/10Programming or data input circuits
    • G11C16/12Programming voltage switching circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/08Address circuits; Decoders; Word-line control circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/10Programming or data input circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/30Power supply circuits

Landscapes

  • Read Only Memory (AREA)

Abstract

PURPOSE:To reduce current consumption in case of writing a data, by cutting off a writing circuit corresponding to at least half of non-selected row wires or column wires, among row wires or column wires of a memory cell. CONSTITUTION:To a writing circuit 2 of each line decoder part in the first system 21, a boosting signal H1 is supplied from the first boosting circuit 23, and the writing circuit 2 of each line decoder part 20 in the second system 22, a boosting signal H2 is supplied from the second boosting circuit 24. When writing a data, one boosting output of the boosting circuits 23, 24 is inhibited under the control based on an input of an address signal, and the writing circuit in one of the first system 21 and the second system 22, that is to say, for instance, a writing circuit corresponding to at least half of row wires being in a non-selected state, among the row wires is cut off.
JP8546681A 1981-03-03 1981-06-03 Non-volatile semiconductor memory Pending JPS57200997A (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP8546681A JPS57200997A (en) 1981-06-03 1981-06-03 Non-volatile semiconductor memory
GB8205687A GB2094086B (en) 1981-03-03 1982-02-26 Non-volatile semiconductor memory system
US06/353,515 US4506350A (en) 1981-03-03 1982-03-01 Non-volatile semiconductor memory system
DE3207485A DE3207485C2 (en) 1981-03-03 1982-03-02 Non-volatile semiconductor memory device
DE3249671A DE3249671C2 (en) 1981-03-03 1982-03-02
US06/630,863 US4597062A (en) 1981-03-03 1984-07-16 Non-volatile semiconductor memory system
GB08420735A GB2144006B (en) 1981-03-03 1984-08-15 Non-volatile semiconductor memory system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8546681A JPS57200997A (en) 1981-06-03 1981-06-03 Non-volatile semiconductor memory

Publications (1)

Publication Number Publication Date
JPS57200997A true JPS57200997A (en) 1982-12-09

Family

ID=13859659

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8546681A Pending JPS57200997A (en) 1981-03-03 1981-06-03 Non-volatile semiconductor memory

Country Status (1)

Country Link
JP (1) JPS57200997A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6069897A (en) * 1983-09-08 1985-04-20 Toshiba Corp Non-volatile semiconductor memory device
JPH08227593A (en) * 1994-11-15 1996-09-03 Sgs Thomson Microelectron Ltd Integrated circuit storage device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6069897A (en) * 1983-09-08 1985-04-20 Toshiba Corp Non-volatile semiconductor memory device
JPS6322393B2 (en) * 1983-09-08 1988-05-11 Toshiba Kk
JPH08227593A (en) * 1994-11-15 1996-09-03 Sgs Thomson Microelectron Ltd Integrated circuit storage device

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