JPS57168367A - Handshake method of master central processing unit and slave central processing unit - Google Patents

Handshake method of master central processing unit and slave central processing unit

Info

Publication number
JPS57168367A
JPS57168367A JP5355481A JP5355481A JPS57168367A JP S57168367 A JPS57168367 A JP S57168367A JP 5355481 A JP5355481 A JP 5355481A JP 5355481 A JP5355481 A JP 5355481A JP S57168367 A JPS57168367 A JP S57168367A
Authority
JP
Japan
Prior art keywords
cpu
power supply
electric power
processing unit
central processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5355481A
Other languages
Japanese (ja)
Inventor
Kazumasa Kumakura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP5355481A priority Critical patent/JPS57168367A/en
Publication of JPS57168367A publication Critical patent/JPS57168367A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To decide a start time point for receiving an instruction, by outputting a power-on signal of a main electric power supply part and a power-on reset signal to a master CPU, from a port of a slave CPU, when the slave CPU has detected a power-on factor of the main electric power supply part. CONSTITUTION:At the time of standby, only a standby electric power supply side shown on the left in the figure is operated, and a slave CPU 1 always monitors a factor of turn-on of a main electric power supply. When the factor of turn-on is detected, the CPU 1 outputs a turn-on signal POWER ON of the main electric power supply through its output port 4, and simultaneously outputs a POWER ON reset signal to a master CPU 3. This reset signal is reset and released, and when the turn-on factor of the main electric power supply is inquired to the CPU, the CPU 1 generates its factor by data SDATA 0-7, outputs a write signal WR to a hand shaking circuit 2, and returns it to the CPU 3.
JP5355481A 1981-04-09 1981-04-09 Handshake method of master central processing unit and slave central processing unit Pending JPS57168367A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5355481A JPS57168367A (en) 1981-04-09 1981-04-09 Handshake method of master central processing unit and slave central processing unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5355481A JPS57168367A (en) 1981-04-09 1981-04-09 Handshake method of master central processing unit and slave central processing unit

Publications (1)

Publication Number Publication Date
JPS57168367A true JPS57168367A (en) 1982-10-16

Family

ID=12946013

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5355481A Pending JPS57168367A (en) 1981-04-09 1981-04-09 Handshake method of master central processing unit and slave central processing unit

Country Status (1)

Country Link
JP (1) JPS57168367A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59135569A (en) * 1983-01-24 1984-08-03 Sharp Corp Control system of multi-processor
JPS61243379A (en) * 1985-04-22 1986-10-29 Yokogawa Electric Corp Ic test system
JPS62162728U (en) * 1986-03-31 1987-10-16
US4848876A (en) * 1987-04-22 1989-07-18 Brother Kogyo Kabushiki Kaisha Electronic control circuit for preventing abnormal operation of a slave control circuit
EP3462279A1 (en) * 2017-09-28 2019-04-03 INTEL Corporation Techniques to dynamically enable and disable accelerator devices in compute environments

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59135569A (en) * 1983-01-24 1984-08-03 Sharp Corp Control system of multi-processor
JPS61243379A (en) * 1985-04-22 1986-10-29 Yokogawa Electric Corp Ic test system
JPS62162728U (en) * 1986-03-31 1987-10-16
US4848876A (en) * 1987-04-22 1989-07-18 Brother Kogyo Kabushiki Kaisha Electronic control circuit for preventing abnormal operation of a slave control circuit
EP3462279A1 (en) * 2017-09-28 2019-04-03 INTEL Corporation Techniques to dynamically enable and disable accelerator devices in compute environments
US11157064B2 (en) 2017-09-28 2021-10-26 Intel Corporation Techniques to dynamically enable and disable accelerator devices in compute environments

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