JPS57166760A - Packet multiplexer - Google Patents
Packet multiplexerInfo
- Publication number
- JPS57166760A JPS57166760A JP56052677A JP5267781A JPS57166760A JP S57166760 A JPS57166760 A JP S57166760A JP 56052677 A JP56052677 A JP 56052677A JP 5267781 A JP5267781 A JP 5267781A JP S57166760 A JPS57166760 A JP S57166760A
- Authority
- JP
- Japan
- Prior art keywords
- information
- signals
- value
- inputted
- standard value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
PURPOSE:To prevent the entitled device from the generation of call loss due to the difference of the quantity of information by connecting a means receiving all calls only when the calls do not exceed a predetermined definite value. CONSTITUTION:Signals on signal lines a1-A1 are inputted to buffer storage circuits b1-bN and simultaneously inputted also to an information quantity calculating circuit 4, which calculates the quantity of information of inputted signals per unit time and sends the calculated result to an information quantity storage circuit 5. A comparator 6 compares the output value from the storage circuit 5 with the standard value and, if the stored value is within the standard value, ''1'' is outputted and, when larger than the standard value, ''0'' is outputted. Signal transmitters C1-CN send reception disabling signals and the receiving signals to the calling side in case of ''0''. A multiplexing circuit 3 selects one of the outputs from the buffer storage circuits b1-bN under the control of a controlling device 8 and outputs the selected one to a terminal 9.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56052677A JPS57166760A (en) | 1981-04-08 | 1981-04-08 | Packet multiplexer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56052677A JPS57166760A (en) | 1981-04-08 | 1981-04-08 | Packet multiplexer |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57166760A true JPS57166760A (en) | 1982-10-14 |
JPH0224059B2 JPH0224059B2 (en) | 1990-05-28 |
Family
ID=12921506
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56052677A Granted JPS57166760A (en) | 1981-04-08 | 1981-04-08 | Packet multiplexer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57166760A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH024074A (en) * | 1987-12-23 | 1990-01-09 | Alcatel Nv | Regulating multiplexer |
-
1981
- 1981-04-08 JP JP56052677A patent/JPS57166760A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH024074A (en) * | 1987-12-23 | 1990-01-09 | Alcatel Nv | Regulating multiplexer |
Also Published As
Publication number | Publication date |
---|---|
JPH0224059B2 (en) | 1990-05-28 |
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