JPS57162162A - Multiplex virtual space data processing system - Google Patents

Multiplex virtual space data processing system

Info

Publication number
JPS57162162A
JPS57162162A JP56044889A JP4488981A JPS57162162A JP S57162162 A JPS57162162 A JP S57162162A JP 56044889 A JP56044889 A JP 56044889A JP 4488981 A JP4488981 A JP 4488981A JP S57162162 A JPS57162162 A JP S57162162A
Authority
JP
Japan
Prior art keywords
segment table
data processing
processing system
virtual space
control register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56044889A
Other languages
Japanese (ja)
Inventor
Akira Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56044889A priority Critical patent/JPS57162162A/en
Publication of JPS57162162A publication Critical patent/JPS57162162A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To increase size of space usable freely by the user, and to freely cope with the increase in a system common area, storing a system common area with one imaginary space. CONSTITUTION:At the access corresponding to a common area, a control register 5-0 is used with the content of a switching register 8, and a control register 5-1 is used with the content of the switching register 8 at the access corresponding to the user's area. When the control register 5-0 is used, a #0 segment table is instructed and offset amount in a segment table 6-0 is given with a part of bits of an execution address 4. When the control register 5-1 is used, #1 segment table is instructed and the offset amount in the segment table 6-1 is given with a part of bits of the execution address 4.
JP56044889A 1981-03-27 1981-03-27 Multiplex virtual space data processing system Pending JPS57162162A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56044889A JPS57162162A (en) 1981-03-27 1981-03-27 Multiplex virtual space data processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56044889A JPS57162162A (en) 1981-03-27 1981-03-27 Multiplex virtual space data processing system

Publications (1)

Publication Number Publication Date
JPS57162162A true JPS57162162A (en) 1982-10-05

Family

ID=12704043

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56044889A Pending JPS57162162A (en) 1981-03-27 1981-03-27 Multiplex virtual space data processing system

Country Status (1)

Country Link
JP (1) JPS57162162A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59124077A (en) * 1982-12-28 1984-07-18 フランス国 Memory management system for processor or microprocessor
JPS60225950A (en) * 1984-04-25 1985-11-11 Hitachi Ltd Controlling system of virtual storage
JPS62182862A (en) * 1985-12-13 1987-08-11 エルサグ　ベイリイ　ソチエタ　ペル　アツィオニ Large capacity memory and multiprocessor including the same
JPH01228027A (en) * 1988-02-10 1989-09-12 Internatl Business Mach Corp <Ibm> Address space management

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59124077A (en) * 1982-12-28 1984-07-18 フランス国 Memory management system for processor or microprocessor
JPS60225950A (en) * 1984-04-25 1985-11-11 Hitachi Ltd Controlling system of virtual storage
JPH0319977B2 (en) * 1984-04-25 1991-03-18 Hitachi Ltd
JPS62182862A (en) * 1985-12-13 1987-08-11 エルサグ　ベイリイ　ソチエタ　ペル　アツィオニ Large capacity memory and multiprocessor including the same
JPH01228027A (en) * 1988-02-10 1989-09-12 Internatl Business Mach Corp <Ibm> Address space management

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