JPS57137949A - Error recovery system of logical device - Google Patents
Error recovery system of logical deviceInfo
- Publication number
- JPS57137949A JPS57137949A JP56022553A JP2255381A JPS57137949A JP S57137949 A JPS57137949 A JP S57137949A JP 56022553 A JP56022553 A JP 56022553A JP 2255381 A JP2255381 A JP 2255381A JP S57137949 A JPS57137949 A JP S57137949A
- Authority
- JP
- Japan
- Prior art keywords
- instruction
- cpu10
- executed
- stand
- cpu20
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Retry When Errors Occur (AREA)
- Hardware Redundancy (AREA)
- Multi Processors (AREA)
Abstract
PURPOSE:To recover a fixed fault, by processing by use of a CPU having no error succeedingly, the processing which has been executed by a faulty CPU, at each instruction unit. CONSTITUTION:When an instruction is executed in a CPU10, information of a program controllable register group 130 before executing the instruction is waited in a stand-by register group 140 whenever one instruction is executed. A retry controlling circuit 260 for the CPU10 on a CPU20 monitors whether retry is executed or not at every instruction. When it is informed to the CPU10 from the retry controlling circut 260 that a recovery impossible error has been detected, an execution controlling circuit 210 of the CPU20 generates an instruction, and informs the control program of a recovery request of the CPU10. The control program halts the processing which is being executed, and executes its transfer. An inter-register shift controlling circuit 270 shift the information to the stand-by register group 240 of the CPU20 from the stand-by regiter group 140 of the CPU10.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56022553A JPS57137949A (en) | 1981-02-18 | 1981-02-18 | Error recovery system of logical device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56022553A JPS57137949A (en) | 1981-02-18 | 1981-02-18 | Error recovery system of logical device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57137949A true JPS57137949A (en) | 1982-08-25 |
JPS6128141B2 JPS6128141B2 (en) | 1986-06-28 |
Family
ID=12086030
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56022553A Granted JPS57137949A (en) | 1981-02-18 | 1981-02-18 | Error recovery system of logical device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57137949A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6341943A (en) * | 1986-08-08 | 1988-02-23 | Nec Corp | Error restoring system for logic unit |
JPH04213736A (en) * | 1990-02-08 | 1992-08-04 | Internatl Business Mach Corp <Ibm> | Check point mechanism for fault tolerant system |
JPH06236289A (en) * | 1993-02-08 | 1994-08-23 | Kofu Nippon Denki Kk | Information processor |
JPH08329026A (en) * | 1995-06-05 | 1996-12-13 | Nec Corp | Dual processor system |
-
1981
- 1981-02-18 JP JP56022553A patent/JPS57137949A/en active Granted
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6341943A (en) * | 1986-08-08 | 1988-02-23 | Nec Corp | Error restoring system for logic unit |
JPH04213736A (en) * | 1990-02-08 | 1992-08-04 | Internatl Business Mach Corp <Ibm> | Check point mechanism for fault tolerant system |
JPH06236289A (en) * | 1993-02-08 | 1994-08-23 | Kofu Nippon Denki Kk | Information processor |
JPH08329026A (en) * | 1995-06-05 | 1996-12-13 | Nec Corp | Dual processor system |
Also Published As
Publication number | Publication date |
---|---|
JPS6128141B2 (en) | 1986-06-28 |
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