JPS57109469A - Video gain controlling circuit - Google Patents

Video gain controlling circuit

Info

Publication number
JPS57109469A
JPS57109469A JP18589080A JP18589080A JPS57109469A JP S57109469 A JPS57109469 A JP S57109469A JP 18589080 A JP18589080 A JP 18589080A JP 18589080 A JP18589080 A JP 18589080A JP S57109469 A JPS57109469 A JP S57109469A
Authority
JP
Japan
Prior art keywords
output
shift register
gain
inverter
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18589080A
Other languages
Japanese (ja)
Inventor
Akihiko Minami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP18589080A priority Critical patent/JPS57109469A/en
Publication of JPS57109469A publication Critical patent/JPS57109469A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/222—Studio circuitry; Studio devices; Studio equipment
    • H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
    • H04N5/2622—Signal amplitude transition in the zone between image portions, e.g. soft edges

Abstract

PURPOSE:To always hold and inclination of an edge part at a constant state by giving priority to a level of the gain, and also to vary the gain smoothly and continuously. CONSTITUTION:A rise timing pulse 1a of a key signal is inputted to a shift register 1. A fall timing pulse 2a of a delayed key signal is inputted to a shift register 2. An output of the shift register 1 is supplied in order to NOR circuits 10, 9 and 8, and an output of the shift register 2 is provided to the NOR circuits 8, 9 and 10. When an FF3 is set by the output of the shift register 1, an output of the FF3 is provided to an inverter 5, an output of the inverter 5 becomes logical ''0'', and a control level of a video signal is held at a prescribed value. On the other hand, since an FF4 is reset, an output of the FF4 becomes logical ''0'', an output of an inverter 7 becomes logical ''1'', and is provided to a priority encoder 6. The gain of the lowest gain level is outputted as a code by the encoder 6.
JP18589080A 1980-12-26 1980-12-26 Video gain controlling circuit Pending JPS57109469A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18589080A JPS57109469A (en) 1980-12-26 1980-12-26 Video gain controlling circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18589080A JPS57109469A (en) 1980-12-26 1980-12-26 Video gain controlling circuit

Publications (1)

Publication Number Publication Date
JPS57109469A true JPS57109469A (en) 1982-07-07

Family

ID=16178665

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18589080A Pending JPS57109469A (en) 1980-12-26 1980-12-26 Video gain controlling circuit

Country Status (1)

Country Link
JP (1) JPS57109469A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59198494A (en) * 1983-04-08 1984-11-10 アムペックス　コーポレーション Font calling system
JPS6179961A (en) * 1984-09-28 1986-04-23 株式会社日立製作所 Absorption type refrigeration cycle

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59198494A (en) * 1983-04-08 1984-11-10 アムペックス　コーポレーション Font calling system
JPS6179961A (en) * 1984-09-28 1986-04-23 株式会社日立製作所 Absorption type refrigeration cycle

Similar Documents

Publication Publication Date Title
JPS57171868A (en) Waveform shaping circuit
EP0084247A3 (en) Operation mode setting circuitry for microprocessor
JPS56136054A (en) Function assigning circuit
ES8304675A1 (en) A digital automatic gain control circuit.
JPS56152372A (en) Laser recording device
JPS57109469A (en) Video gain controlling circuit
ATE40026T1 (en) LOSS CORRECTION CIRCUIT FOR CORRECTING VIDEO SIGNALS DISTURBED BY LOSSES.
JPS54119902A (en) Pause time limiter for disc reproducer
EP0298747A3 (en) Register
JPS5597633A (en) Keyboard control circuit
JPS5370653A (en) Digital output unit
JPS56117423A (en) Binary coding circuit by multistage threshold level
JPS57150221A (en) On and off detecting circuit of switch
JPS54113236A (en) Logical signal transfer circuit
JPS6410742A (en) Digital signal transmission system
JPS5599610A (en) Digital proportional receiver
JPS552927A (en) Automatic time correction device
JPS5793721A (en) Schmitt circuit
JPS57113101A (en) Fault-output preventing circuit of control circuit
JPS5726931A (en) Programmable counter
JPS51118356A (en) Gain control circuit
JPS5275236A (en) Signal processing circuit
JPS54528A (en) Digital input unit
JPS57129020A (en) Signal processing circuit
JPS53136807A (en) Timer recording circuit