JPS5658113A - Data delaying device - Google Patents

Data delaying device

Info

Publication number
JPS5658113A
JPS5658113A JP13205779A JP13205779A JPS5658113A JP S5658113 A JPS5658113 A JP S5658113A JP 13205779 A JP13205779 A JP 13205779A JP 13205779 A JP13205779 A JP 13205779A JP S5658113 A JPS5658113 A JP S5658113A
Authority
JP
Japan
Prior art keywords
circuit
supplied
terminal
output
well
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13205779A
Other languages
Japanese (ja)
Other versions
JPS6336049B2 (en
Inventor
Tadashi Kojima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP13205779A priority Critical patent/JPS5658113A/en
Publication of JPS5658113A publication Critical patent/JPS5658113A/en
Publication of JPS6336049B2 publication Critical patent/JPS6336049B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10527—Audio or video recording; Data buffering arrangements

Abstract

PURPOSE:To eliminate the initial setting when the counting is started, by reducing the number of address counters down to one. CONSTITUTION:The record signal supplied from the video tape recorder is supplied to the data input terminal IN of the RAM34 from the input terminal 39 via the data isolating circuit 40 as well as to the synchronous isolating circuit 41. The 1st output of the circuit 41 is supplied to the R/W control circuit 35, and the 2nd output is supplied to the address counter 28 as well as to the down input of the buffer counter 30. The 3rd output of the circuit 41 is supplied to the control terminal of the phase synchronous loop 42 as well as to the 1st control terminal of the read timing control circuit 43. The count output of the counter 30 is supplied to the 3rd control terminal of the read timing control circuit 43 via the detection circuit 46. The writing word Wwd delivered from the circuit 41 is supplied to the terminal 37, and the reading word Rwd delivered from the circuit 43 is supplied to the terminal 38 respectively.
JP13205779A 1979-10-13 1979-10-13 Data delaying device Granted JPS5658113A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13205779A JPS5658113A (en) 1979-10-13 1979-10-13 Data delaying device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13205779A JPS5658113A (en) 1979-10-13 1979-10-13 Data delaying device

Publications (2)

Publication Number Publication Date
JPS5658113A true JPS5658113A (en) 1981-05-21
JPS6336049B2 JPS6336049B2 (en) 1988-07-19

Family

ID=15072501

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13205779A Granted JPS5658113A (en) 1979-10-13 1979-10-13 Data delaying device

Country Status (1)

Country Link
JP (1) JPS5658113A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58125210A (en) * 1982-01-20 1983-07-26 Pioneer Electronic Corp Device for producing memory address information signal
JPS58139385A (en) * 1982-02-10 1983-08-18 Pioneer Electronic Corp Information signal generator for memory address
JPS58161114A (en) * 1982-03-19 1983-09-24 Pioneer Electronic Corp Memory address information signal generating device
JPS58211310A (en) * 1982-05-31 1983-12-08 Akai Electric Co Ltd Signal processing method of pcm recording and reproducing device
JPS59152509A (en) * 1983-02-18 1984-08-31 Sanyo Electric Co Ltd Muting device
JPS61107576A (en) * 1984-10-31 1986-05-26 Toshiba Corp Control method for deinterleave processing memory in digital reproducing device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58125210A (en) * 1982-01-20 1983-07-26 Pioneer Electronic Corp Device for producing memory address information signal
JPS58139385A (en) * 1982-02-10 1983-08-18 Pioneer Electronic Corp Information signal generator for memory address
JPS58161114A (en) * 1982-03-19 1983-09-24 Pioneer Electronic Corp Memory address information signal generating device
JPS58211310A (en) * 1982-05-31 1983-12-08 Akai Electric Co Ltd Signal processing method of pcm recording and reproducing device
JPS59152509A (en) * 1983-02-18 1984-08-31 Sanyo Electric Co Ltd Muting device
JPS61107576A (en) * 1984-10-31 1986-05-26 Toshiba Corp Control method for deinterleave processing memory in digital reproducing device

Also Published As

Publication number Publication date
JPS6336049B2 (en) 1988-07-19

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