JPS5636251A - Information communication system - Google Patents

Information communication system

Info

Publication number
JPS5636251A
JPS5636251A JP11325279A JP11325279A JPS5636251A JP S5636251 A JPS5636251 A JP S5636251A JP 11325279 A JP11325279 A JP 11325279A JP 11325279 A JP11325279 A JP 11325279A JP S5636251 A JPS5636251 A JP S5636251A
Authority
JP
Japan
Prior art keywords
data
address
memories
transmission
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11325279A
Other languages
Japanese (ja)
Inventor
Tadanobu Okada
Katsuharu Tsukamoto
Makoto Matsumoto
Takao Hayamizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Panasonic System Solutions Japan Co Ltd
Original Assignee
Matsushita Graphic Communication Systems Inc
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Graphic Communication Systems Inc, Nippon Telegraph and Telephone Corp filed Critical Matsushita Graphic Communication Systems Inc
Priority to JP11325279A priority Critical patent/JPS5636251A/en
Publication of JPS5636251A publication Critical patent/JPS5636251A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/24—Time-division multiplex systems in which the allocation is indicated by an address the different channels being transmitted sequentially

Abstract

PURPOSE:To make it possible to transmit data between plural kinds of I/O devices simultaneously with the same transmission line, by adding an address indicating the type of a device. CONSTITUTION:Data from facsimile transmission unit 1 and keyboard device 2 are stored in memories 4 and 3 respectively. When the information volume reaches a prescribed value, flip flops 7 and 5 are set by a control signal. When receiving this set output, control circuit 9 controls to transfer data stored in memories 4 and 3 to address information adding circuits 13 and 12. Address signals indicating that these data are input from facsimile transmission unit 1 and keyboard device 2 are added to the beginning of data by circuits 13 and 14, and data are transmitted to transmission line LN through transmission circuit 14. In the receiving side, address signals above are discriminated, and the output device corresponding to the transmission-side device receives data.
JP11325279A 1979-09-03 1979-09-03 Information communication system Pending JPS5636251A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11325279A JPS5636251A (en) 1979-09-03 1979-09-03 Information communication system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11325279A JPS5636251A (en) 1979-09-03 1979-09-03 Information communication system

Publications (1)

Publication Number Publication Date
JPS5636251A true JPS5636251A (en) 1981-04-09

Family

ID=14607430

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11325279A Pending JPS5636251A (en) 1979-09-03 1979-09-03 Information communication system

Country Status (1)

Country Link
JP (1) JPS5636251A (en)

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