JPS56157181A - High-grade television picture receiver - Google Patents
High-grade television picture receiverInfo
- Publication number
- JPS56157181A JPS56157181A JP6088680A JP6088680A JPS56157181A JP S56157181 A JPS56157181 A JP S56157181A JP 6088680 A JP6088680 A JP 6088680A JP 6088680 A JP6088680 A JP 6088680A JP S56157181 A JPS56157181 A JP S56157181A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- horizontal
- video signal
- signal
- time axis
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
Abstract
PURPOSE:To realize a common use among a horizontal deflecting circuit, a convergence circuit, a pincushion compensating circuit and others, by compressing a video signal of the using standard system down to 1/2 in time axis and thus realizing a reception of the video signal of present NTSC system. CONSTITUTION:A high-grade TV signal is demodulated by its demodulating circuit 46 and applied to a CRT19 via the switches SW3-SW5 to ensure a high-precision projection of an image having (2N+a) pieces of scanning lines (N: scanning number of standard type; a: an integer). Both the horizontal and vertical signals separated by a synchronous separating circuit 3 of the demodulating circuit 46 are supplied to a deflecting coil 23 via the horizontal and vertical deflecting circuits 22 and 25 and the switches SW1-SW2. At the same time, the using NTSC signal is applied to a synchronous axis compression delaying circuit 26, a burst gate 29 and a synchronous separating circuit 27 respectively. Then the 1H period of each line of a composite video signal is compressed to a 1/2 in time axis and then decoded through a decoding circuit 47 of the NTSC signal subjected to time axis compression.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6088680A JPS56157181A (en) | 1980-05-07 | 1980-05-07 | High-grade television picture receiver |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6088680A JPS56157181A (en) | 1980-05-07 | 1980-05-07 | High-grade television picture receiver |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56157181A true JPS56157181A (en) | 1981-12-04 |
Family
ID=13155292
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6088680A Pending JPS56157181A (en) | 1980-05-07 | 1980-05-07 | High-grade television picture receiver |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56157181A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6154775A (en) * | 1984-08-24 | 1986-03-19 | Nec Home Electronics Ltd | Synchronizing separation method |
-
1980
- 1980-05-07 JP JP6088680A patent/JPS56157181A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6154775A (en) * | 1984-08-24 | 1986-03-19 | Nec Home Electronics Ltd | Synchronizing separation method |
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