JPS56147221A - System clock generating circuit in integrated circuit - Google Patents

System clock generating circuit in integrated circuit

Info

Publication number
JPS56147221A
JPS56147221A JP5108180A JP5108180A JPS56147221A JP S56147221 A JPS56147221 A JP S56147221A JP 5108180 A JP5108180 A JP 5108180A JP 5108180 A JP5108180 A JP 5108180A JP S56147221 A JPS56147221 A JP S56147221A
Authority
JP
Japan
Prior art keywords
generating circuit
gates
power consumption
circuit
sck
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5108180A
Other languages
Japanese (ja)
Other versions
JPS6148727B2 (en
Inventor
Yoshikazu Nishiura
Takiji Mineyama
Kazuo Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP5108180A priority Critical patent/JPS56147221A/en
Priority to US06/254,543 priority patent/US4463440A/en
Publication of JPS56147221A publication Critical patent/JPS56147221A/en
Publication of JPS6148727B2 publication Critical patent/JPS6148727B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/03—Astable circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/06—Clock generators producing several clock signals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Sources (AREA)
  • Calculators And Similar Devices (AREA)

Abstract

PURPOSE:To reduce power consumption of the system clock SCK generating circuit, by controlling generation and stopping of basic CK by the control signal from the static (CK) control (CT) signal generating circuit. CONSTITUTION:Basic CK generating circuit H stops the operation by control signal ST generated by the CKCT signal generating circuit consisting of D type FFs 3 and 6, RS FFs 4 and 5, OR gates, inverters and AND gates, and signals A', A, B' and B derived from inverters I1-I4 are held in states 1, 0, 1 and 0, and power is not consumed. When the reset input of FF5 is 0, control signal SL becomes 1 and is given to OR gates 21-25 of the SCK generating circuit, and SCKs phi1-phi5 are held in state 1, and power consumption is reduced. When the system is in the holding state, signals ST and SL are generated by an instruction to stop SCK for circuits other than minimum circuits, and the CKCT signal generating circuit is constituted with a static logical operation circuit, thus power consumption is reduced.
JP5108180A 1980-04-15 1980-04-15 System clock generating circuit in integrated circuit Granted JPS56147221A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP5108180A JPS56147221A (en) 1980-04-15 1980-04-15 System clock generating circuit in integrated circuit
US06/254,543 US4463440A (en) 1980-04-15 1981-04-15 System clock generator in integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5108180A JPS56147221A (en) 1980-04-15 1980-04-15 System clock generating circuit in integrated circuit

Publications (2)

Publication Number Publication Date
JPS56147221A true JPS56147221A (en) 1981-11-16
JPS6148727B2 JPS6148727B2 (en) 1986-10-25

Family

ID=12876857

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5108180A Granted JPS56147221A (en) 1980-04-15 1980-04-15 System clock generating circuit in integrated circuit

Country Status (1)

Country Link
JP (1) JPS56147221A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5548765A (en) * 1990-08-28 1996-08-20 Seiko Epson Corporation Power saving display subsystem for portable computers

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52149432A (en) * 1976-06-08 1977-12-12 Toshiba Corp Electronic device
JPS5312247A (en) * 1976-07-21 1978-02-03 Toshiba Corp Electronic desk computer with clock
JPS5368051A (en) * 1976-11-29 1978-06-17 Sharp Corp Integrated circuit device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52149432A (en) * 1976-06-08 1977-12-12 Toshiba Corp Electronic device
JPS5312247A (en) * 1976-07-21 1978-02-03 Toshiba Corp Electronic desk computer with clock
JPS5368051A (en) * 1976-11-29 1978-06-17 Sharp Corp Integrated circuit device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5548765A (en) * 1990-08-28 1996-08-20 Seiko Epson Corporation Power saving display subsystem for portable computers

Also Published As

Publication number Publication date
JPS6148727B2 (en) 1986-10-25

Similar Documents

Publication Publication Date Title
JPS56147221A (en) System clock generating circuit in integrated circuit
JPS5642827A (en) Data processor
JPS57113169A (en) Microcomputer
JPS57158095A (en) Shift register circuit
JPS54107234A (en) Information processing unit
JPS57150221A (en) On and off detecting circuit of switch
JPS5760422A (en) Data transfer controlling system
JPS55132155A (en) Phase control circuit
JPS5647826A (en) Waveform generator
JPS56114441A (en) Counting circuit
JPS5374467A (en) Electronic watch
JPS5312247A (en) Electronic desk computer with clock
JPS57106962A (en) Data processor
JPS576918A (en) Clock control circuit
JPS56168250A (en) Data holding circuit of information processor
JPS5746395A (en) Integrated circuit
JPS5776915A (en) Logical circuit for trigger control
JPS55112039A (en) Logic circuit
JPS5533229A (en) Status control system of miniature electronic computer
JPS5644882A (en) Time generating device
JPS5349923A (en) Electronic desk-top computer
JPS57130284A (en) Magnetic bubble memory device
JPS5588170A (en) Actuation system of process controller output unit
JPS53121532A (en) 1-bit delay type full adder
JPS5317953A (en) Generator circuit for stabilized control output