JPS55132155A - Phase control circuit - Google Patents
Phase control circuitInfo
- Publication number
- JPS55132155A JPS55132155A JP3770979A JP3770979A JPS55132155A JP S55132155 A JPS55132155 A JP S55132155A JP 3770979 A JP3770979 A JP 3770979A JP 3770979 A JP3770979 A JP 3770979A JP S55132155 A JPS55132155 A JP S55132155A
- Authority
- JP
- Japan
- Prior art keywords
- clocks
- clock
- read
- write
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/05—Electric or magnetic storage of signals before transmitting or retransmitting for changing the transmission rate
Abstract
PURPOSE:To make it possible to maintain a fixed phase relation between write and read clocks by controlling an inhibiting circuit for read clocks by exercising a supervision over whether clocks are supplied to write and read counters. CONSTITUTION:Once input data and the 1st and 2nd clocks are applied to terminals 11, 12 and 13, write and read counters 19 and 20 start operating. When a phase difference between write clock WD and read clock RD exceeds a fixed value, inhibiting pulse generating circuit 30 supplies inhibiting pulse IH to FF31 and gates 37 and 32 inhibits the 2nd clock from passing through. While the 1st and 2nd clocks are supplied, clock OFF detecting circuits 33 and 34 send their outputs to eliminate the output of gate 36. The output of gate 36 is delayed 38 as long as the phase difference between clocks WD and RD reaches the fixed value and led to gate 37. Therefore, when clocks WD and RD bears the fixed phase relation, the phase control of circuit 30 is never performed unitl either the 1st or 2nd clock is interrupted.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3770979A JPS55132155A (en) | 1979-03-31 | 1979-03-31 | Phase control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3770979A JPS55132155A (en) | 1979-03-31 | 1979-03-31 | Phase control circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS55132155A true JPS55132155A (en) | 1980-10-14 |
Family
ID=12505042
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3770979A Pending JPS55132155A (en) | 1979-03-31 | 1979-03-31 | Phase control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55132155A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6051338A (en) * | 1983-07-11 | 1985-03-22 | インタ−ナシヨナル スタンダ−ド エレクトリツク コ−ポレイシヨン | Arrival time instructing device of reception signal |
| US6445656B1 (en) * | 1999-04-13 | 2002-09-03 | Ricoh Company, Ltd. | Optical recording/reproducing method and apparatus for optical storage media |
-
1979
- 1979-03-31 JP JP3770979A patent/JPS55132155A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6051338A (en) * | 1983-07-11 | 1985-03-22 | インタ−ナシヨナル スタンダ−ド エレクトリツク コ−ポレイシヨン | Arrival time instructing device of reception signal |
| JPH0362332B2 (en) * | 1983-07-11 | 1991-09-25 | Intaanashonaru Sutandaado Erekutoritsuku Corp | |
| US6445656B1 (en) * | 1999-04-13 | 2002-09-03 | Ricoh Company, Ltd. | Optical recording/reproducing method and apparatus for optical storage media |
| US6738328B2 (en) | 1999-04-13 | 2004-05-18 | Ricoh Company, Ltd. | Optical recording/reproducing method and apparatus for optical storage media |
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