JPS5614340A - Communication control system - Google Patents

Communication control system

Info

Publication number
JPS5614340A
JPS5614340A JP8813579A JP8813579A JPS5614340A JP S5614340 A JPS5614340 A JP S5614340A JP 8813579 A JP8813579 A JP 8813579A JP 8813579 A JP8813579 A JP 8813579A JP S5614340 A JPS5614340 A JP S5614340A
Authority
JP
Japan
Prior art keywords
buffer
memory
control unit
unit
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8813579A
Other languages
Japanese (ja)
Inventor
Yoshinori Tsujita
Shigetoshi Suwa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP8813579A priority Critical patent/JPS5614340A/en
Publication of JPS5614340A publication Critical patent/JPS5614340A/en
Pending legal-status Critical Current

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  • Communication Control (AREA)

Abstract

PURPOSE: To control many communication lines with one control unit, by transferring directly receiving data from the communication control unit to the buffer for message processing on the main memory and by eliminating the buffer for editing on the main memory.
CONSTITUTION: Main memory 3 and communication control unit 1 are connected by data bus 73 to transfer directly receiving data from unit 1 to receiving buffer 74 for message processing on memory 3. That is, byte assembling and decomposing part 51 of unit 1 monitors receiving data from communication line 52, and reports detection of the start flag pattern to control part 54 when the start flag pattern is detected. Control part 54 updates contents of memory block designating part 59. When data receiving of frames is started, addresses, information, and so on are transferred from the memory block, which is designated by designating part 59, to buffer 74 on memory 3. As a result, the buffer for editing on memory 3 can be eliminated, and many communication lines can be controlled by one control unit.
COPYRIGHT: (C)1981,JPO&Japio
JP8813579A 1979-07-13 1979-07-13 Communication control system Pending JPS5614340A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8813579A JPS5614340A (en) 1979-07-13 1979-07-13 Communication control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8813579A JPS5614340A (en) 1979-07-13 1979-07-13 Communication control system

Publications (1)

Publication Number Publication Date
JPS5614340A true JPS5614340A (en) 1981-02-12

Family

ID=13934478

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8813579A Pending JPS5614340A (en) 1979-07-13 1979-07-13 Communication control system

Country Status (1)

Country Link
JP (1) JPS5614340A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6238239A (en) * 1985-08-08 1987-02-19 Jgc Corp Catalyst for steam reforming of hydrocarbon

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6238239A (en) * 1985-08-08 1987-02-19 Jgc Corp Catalyst for steam reforming of hydrocarbon
JPH054134B2 (en) * 1985-08-08 1993-01-19 Jgc Corp

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