JPS5537680A - Decentralized control system - Google Patents

Decentralized control system

Info

Publication number
JPS5537680A
JPS5537680A JP11100978A JP11100978A JPS5537680A JP S5537680 A JPS5537680 A JP S5537680A JP 11100978 A JP11100978 A JP 11100978A JP 11100978 A JP11100978 A JP 11100978A JP S5537680 A JPS5537680 A JP S5537680A
Authority
JP
Japan
Prior art keywords
memory
decentralized control
processors
processor
common
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11100978A
Other languages
Japanese (ja)
Inventor
Kunitoshi Sugi
Yoshinori Hori
Yoshihiro Osanai
Yoshiaki Tokita
Kenji Seike
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Original Assignee
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Hitachi Ltd, NEC Corp, Nippon Telegraph and Telephone Corp, Oki Electric Industry Co Ltd, Nippon Electric Co Ltd filed Critical Fujitsu Ltd
Priority to JP11100978A priority Critical patent/JPS5537680A/en
Publication of JPS5537680A publication Critical patent/JPS5537680A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make decentralized control possible without providing a common memory, by storing a state control tape controlling a processing state in a memory in a processor.
CONSTITUTION: Memory units which are arranged corresponding to processors and to and from which data can be written or read in the order of event occurrence are connected to common bus BS which transfers information between processors CP and NP. Since the memory in each processor is stored with state control tape TBL controlling a processing state, a next process is unconditionally determined and no process contradiction occurs. Therefore, the need for a common memory is eliminated and decentralized control can be attained.
COPYRIGHT: (C)1980,JPO&Japio
JP11100978A 1978-09-08 1978-09-08 Decentralized control system Pending JPS5537680A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11100978A JPS5537680A (en) 1978-09-08 1978-09-08 Decentralized control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11100978A JPS5537680A (en) 1978-09-08 1978-09-08 Decentralized control system

Publications (1)

Publication Number Publication Date
JPS5537680A true JPS5537680A (en) 1980-03-15

Family

ID=14550081

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11100978A Pending JPS5537680A (en) 1978-09-08 1978-09-08 Decentralized control system

Country Status (1)

Country Link
JP (1) JPS5537680A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58149557A (en) * 1981-12-02 1983-09-05 エヌ　ベー　フイリップス　フルーイランペン　ファブリケン Multiprocessor system
JPS6256049A (en) * 1985-09-05 1987-03-11 Nippon Telegr & Teleph Corp <Ntt> Method for controlling communication processor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5363833A (en) * 1976-11-18 1978-06-07 Nippon Telegr & Teleph Corp <Ntt> Cyclic buffer receiving system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5363833A (en) * 1976-11-18 1978-06-07 Nippon Telegr & Teleph Corp <Ntt> Cyclic buffer receiving system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58149557A (en) * 1981-12-02 1983-09-05 エヌ　ベー　フイリップス　フルーイランペン　ファブリケン Multiprocessor system
JPS6256049A (en) * 1985-09-05 1987-03-11 Nippon Telegr & Teleph Corp <Ntt> Method for controlling communication processor

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