GB1520484A - Data processing system - Google Patents
Data processing systemInfo
- Publication number
- GB1520484A GB1520484A GB3900775A GB3900775A GB1520484A GB 1520484 A GB1520484 A GB 1520484A GB 3900775 A GB3900775 A GB 3900775A GB 3900775 A GB3900775 A GB 3900775A GB 1520484 A GB1520484 A GB 1520484A
- Authority
- GB
- United Kingdom
- Prior art keywords
- data
- module
- memory
- data transfer
- processor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
Abstract
1520484 Data processing systems DATA GENERAL CORP 23 Sept 1975 [25 Sept 1974] 39007/75 Heading G4 In a system comprising a plurality of memory modules access to a module by a processor may be initiated before transfer of data between the module and the or another processor has been completed, and at least one module has means for sensing when data transfer in respect of the other module has been completed before allowing its own data transfer to take place. Operation of the system is controlled by command signals from the or each processor and status signals from the memory, there being a common address bus and common data transfer bus shared by the memory modules and processors. Each memory module signals when it has the use of the data transfer bus and effectively prevents any other memory module from transferring data. Data may be stored in the memory modules in interleaved fashion. The disclosure is identical to that of Specification 1,520,485.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US50915974A | 1974-09-25 | 1974-09-25 |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1520484A true GB1520484A (en) | 1978-08-09 |
Family
ID=24025532
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB3900775A Expired GB1520484A (en) | 1974-09-25 | 1975-09-23 | Data processing system |
GB21378A Expired GB1520486A (en) | 1974-09-25 | 1975-09-23 | Memory module for data processing system |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB21378A Expired GB1520486A (en) | 1974-09-25 | 1975-09-23 | Memory module for data processing system |
Country Status (6)
Country | Link |
---|---|
JP (1) | JPS5151244A (en) |
AU (1) | AU497876B2 (en) |
CA (1) | CA1051121A (en) |
DE (1) | DE2542102C2 (en) |
GB (2) | GB1520484A (en) |
NL (1) | NL7511288A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5111530A (en) * | 1988-11-04 | 1992-05-05 | Sony Corporation | Digital audio signal generating apparatus |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4298931A (en) * | 1978-06-02 | 1981-11-03 | Hitachi, Ltd. | Character pattern display system |
DE2939412C2 (en) * | 1979-09-28 | 1983-11-17 | Siemens AG, 1000 Berlin und 8000 München | Circuit arrangement for addressing data for read and write access in a data processing system |
US4321667A (en) * | 1979-10-31 | 1982-03-23 | International Business Machines Corp. | Add-on programs with code verification and control |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US26087A (en) * | 1859-11-15 | Improvement in fastening metal hoops on cotton-bales | ||
GB888732A (en) * | 1959-12-30 | |||
JPS4828583A (en) * | 1972-03-24 | 1973-04-16 | ||
US3821709A (en) * | 1972-10-05 | 1974-06-28 | Honeywell Inf Systems | Memory storage sequencer |
US3812473A (en) * | 1972-11-24 | 1974-05-21 | Ibm | Storage system with conflict-free multiple simultaneous access |
-
1975
- 1975-09-19 CA CA235,866A patent/CA1051121A/en not_active Expired
- 1975-09-20 DE DE19752542102 patent/DE2542102C2/en not_active Expired
- 1975-09-23 GB GB3900775A patent/GB1520484A/en not_active Expired
- 1975-09-23 GB GB21378A patent/GB1520486A/en not_active Expired
- 1975-09-23 AU AU85111/75A patent/AU497876B2/en not_active Expired
- 1975-09-25 JP JP11594575A patent/JPS5151244A/en active Granted
- 1975-09-25 NL NL7511288A patent/NL7511288A/en not_active Application Discontinuation
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5111530A (en) * | 1988-11-04 | 1992-05-05 | Sony Corporation | Digital audio signal generating apparatus |
GB2263350A (en) * | 1988-11-04 | 1993-07-21 | Sony Corp | Digital processor for audio signal generator. |
GB2226683B (en) * | 1988-11-04 | 1993-10-06 | Sony Corp | A digital audio signal generating apparatus |
Also Published As
Publication number | Publication date |
---|---|
JPS5151244A (en) | 1976-05-06 |
DE2542102C2 (en) | 1982-10-28 |
GB1520486A (en) | 1978-08-09 |
JPS5731176B2 (en) | 1982-07-02 |
CA1051121A (en) | 1979-03-20 |
AU8511175A (en) | 1977-03-31 |
DE2542102A1 (en) | 1976-04-08 |
NL7511288A (en) | 1976-03-29 |
AU497876B2 (en) | 1979-01-18 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19940923 |