JPS56143049A - Output circuit - Google Patents

Output circuit

Info

Publication number
JPS56143049A
JPS56143049A JP4409380A JP4409380A JPS56143049A JP S56143049 A JPS56143049 A JP S56143049A JP 4409380 A JP4409380 A JP 4409380A JP 4409380 A JP4409380 A JP 4409380A JP S56143049 A JPS56143049 A JP S56143049A
Authority
JP
Japan
Prior art keywords
data
bits
bus
preset
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4409380A
Other languages
Japanese (ja)
Inventor
Takashi Shirae
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Komatsu Ltd
Original Assignee
Komatsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Komatsu Ltd filed Critical Komatsu Ltd
Priority to JP4409380A priority Critical patent/JPS56143049A/en
Publication of JPS56143049A publication Critical patent/JPS56143049A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0615—Address space extension
    • G06F12/0623—Address space extension for memory modules

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To simplify the circuit constitution and to reduce the cost, by simultaneously outputting the data of a number of bits through the use of vacant address space. CONSTITUTION:Data storage in the address space of the memory 10 is designated in the memory area 10A, and a part 10B of vacant area is used as the preset area. If the computer simultaneously outputs the data of the length (e.g., 20 bits) in excess of the data bit length (e.g., 8 bits), the data from the original data bus is preset to the low-order 8 bits of the counter 15 and the data from the address bus to the high-order 12 bias. Further, 1 is set to the most significant bit of the address, to show the address bus as the data bus. The output instruction P0 of the control bus is taken for logarithmic sum with 1 of the most significant bit, and the data is simultaneously preset by adding the counter preset instruction signal Pa to the counter 15. Thus, the register for synchronism can be saved, allowing to simplify the circuit.
JP4409380A 1980-04-04 1980-04-04 Output circuit Pending JPS56143049A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4409380A JPS56143049A (en) 1980-04-04 1980-04-04 Output circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4409380A JPS56143049A (en) 1980-04-04 1980-04-04 Output circuit

Publications (1)

Publication Number Publication Date
JPS56143049A true JPS56143049A (en) 1981-11-07

Family

ID=12681998

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4409380A Pending JPS56143049A (en) 1980-04-04 1980-04-04 Output circuit

Country Status (1)

Country Link
JP (1) JPS56143049A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS608990U (en) * 1983-06-30 1985-01-22 日本電気ホームエレクトロニクス株式会社 Microcomputer system with ROM for character generation
JPS63225836A (en) * 1987-03-13 1988-09-20 Brother Ind Ltd Storage device
JPH02227765A (en) * 1989-01-13 1990-09-10 Internatl Business Mach Corp <Ibm> Data transfer apparatus for digital computer
WO1992014217A1 (en) * 1991-02-05 1992-08-20 Omron Corporation Prom compatible processor and read/write method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS608990U (en) * 1983-06-30 1985-01-22 日本電気ホームエレクトロニクス株式会社 Microcomputer system with ROM for character generation
JPS63225836A (en) * 1987-03-13 1988-09-20 Brother Ind Ltd Storage device
JPH02227765A (en) * 1989-01-13 1990-09-10 Internatl Business Mach Corp <Ibm> Data transfer apparatus for digital computer
WO1992014217A1 (en) * 1991-02-05 1992-08-20 Omron Corporation Prom compatible processor and read/write method thereof

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