JPS56134384A - Memory access system - Google Patents

Memory access system

Info

Publication number
JPS56134384A
JPS56134384A JP3748780A JP3748780A JPS56134384A JP S56134384 A JPS56134384 A JP S56134384A JP 3748780 A JP3748780 A JP 3748780A JP 3748780 A JP3748780 A JP 3748780A JP S56134384 A JPS56134384 A JP S56134384A
Authority
JP
Japan
Prior art keywords
address
memory
bits
converted
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3748780A
Other languages
Japanese (ja)
Inventor
Koichi Ikeda
Mitsuhiro Yamaga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP3748780A priority Critical patent/JPS56134384A/en
Publication of JPS56134384A publication Critical patent/JPS56134384A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To shorten an access time in processing information on a virtual storage system, by dividing an address and inputting the same to a memory as divided and by performing the address conversion and a part of memory access in parallel operation. CONSTITUTION:As virtual address register 5 is set, P bits among the low-order (n) bits, which are not converted, of virtual address 10 are inputted to memory 8 as former half RA. The high-order bits which are converted into the actual address of address 10, on the other hand, are converted by converter 2 and held in actual address register 6 to form latter half CA of the divided address together with the remaining low-order bits of address 10, thereby attaining access to memory 8. Therefore, the address conversion and a part of the memory access are carried out in parallel, so that the memory will be accessed in a shorter time than processing in series.
JP3748780A 1980-03-26 1980-03-26 Memory access system Pending JPS56134384A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3748780A JPS56134384A (en) 1980-03-26 1980-03-26 Memory access system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3748780A JPS56134384A (en) 1980-03-26 1980-03-26 Memory access system

Publications (1)

Publication Number Publication Date
JPS56134384A true JPS56134384A (en) 1981-10-21

Family

ID=12498871

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3748780A Pending JPS56134384A (en) 1980-03-26 1980-03-26 Memory access system

Country Status (1)

Country Link
JP (1) JPS56134384A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60114953A (en) * 1983-10-31 1985-06-21 サン・マイクロシステムズ・インコーポレーテツド Computer unit employing address translation
EP0182501A2 (en) * 1984-11-20 1986-05-28 Tektronix, Inc. Memory mapping method and apparatus

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60114953A (en) * 1983-10-31 1985-06-21 サン・マイクロシステムズ・インコーポレーテツド Computer unit employing address translation
JPH0584532B2 (en) * 1983-10-31 1993-12-02 Sun Microsystems Inc
EP0182501A2 (en) * 1984-11-20 1986-05-28 Tektronix, Inc. Memory mapping method and apparatus

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