JPS56121105A - Sequence controller - Google Patents
Sequence controllerInfo
- Publication number
- JPS56121105A JPS56121105A JP2480180A JP2480180A JPS56121105A JP S56121105 A JPS56121105 A JP S56121105A JP 2480180 A JP2480180 A JP 2480180A JP 2480180 A JP2480180 A JP 2480180A JP S56121105 A JPS56121105 A JP S56121105A
- Authority
- JP
- Japan
- Prior art keywords
- interruption
- external device
- circuit
- signal
- zero
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
- G05B19/054—Input/output
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/10—Plc systems
- G05B2219/11—Plc I-O input output
- G05B2219/1168—Peak amplitude for input, nul amplitude for activating output
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
Abstract
PURPOSE:To simplify the circuit of a sequence controller by permitting a central processor to execute an output instruction in response to the zero-cross timing of a commercial power source. CONSTITUTION:According to a program in program storing device 4, CPU1 performs arithmetic that corresponds to the state of an external device obtained via input device 2, and then transfers the result to the external device via output device 3. The zero-cross point of the commercial power source is detected and on the basis of the detection signal, an interruption signal is generated by interruption generator 7 to permit CPU to make an interruption. In response to the interruption signal, CPU1 executes output instruction successively to send a pulse signal to output device 3, triggering Triacs 35-38. Thus, a latch circuit, etc., for the temporary storage of the state of the external device is unnecessary and the circuit can be simplified.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2480180A JPS56121105A (en) | 1980-02-28 | 1980-02-28 | Sequence controller |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2480180A JPS56121105A (en) | 1980-02-28 | 1980-02-28 | Sequence controller |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56121105A true JPS56121105A (en) | 1981-09-22 |
Family
ID=12148292
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2480180A Pending JPS56121105A (en) | 1980-02-28 | 1980-02-28 | Sequence controller |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56121105A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53122079A (en) * | 1977-03-31 | 1978-10-25 | Sharp Corp | Output controlling system for sequential controller |
-
1980
- 1980-02-28 JP JP2480180A patent/JPS56121105A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53122079A (en) * | 1977-03-31 | 1978-10-25 | Sharp Corp | Output controlling system for sequential controller |
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