JPS5593383A - Processing circuit for television signal - Google Patents

Processing circuit for television signal

Info

Publication number
JPS5593383A
JPS5593383A JP205579A JP205579A JPS5593383A JP S5593383 A JPS5593383 A JP S5593383A JP 205579 A JP205579 A JP 205579A JP 205579 A JP205579 A JP 205579A JP S5593383 A JPS5593383 A JP S5593383A
Authority
JP
Japan
Prior art keywords
potential
interlocking
collector current
video
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP205579A
Other languages
Japanese (ja)
Other versions
JPS6410155B2 (en
Inventor
Yasuta Tomuro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP205579A priority Critical patent/JPS5593383A/en
Publication of JPS5593383A publication Critical patent/JPS5593383A/en
Publication of JPS6410155B2 publication Critical patent/JPS6410155B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To avoid the change in DC potential at the video output signal and the video signal component at the color interlocking output signal, by providing two differential amplifiers, in the circuit electrically interlocking the contrast adjustment and color saturation adjustment.
CONSTITUTION: With the circuit interlocking the contrast adjustment and color saturation adjustment, the first differential amplifier 1 consisting of transistors Tr1a, 1b and the second differential amplifier 21 consisting of Tr21a, 21b and resistors 22, 23, 24 are provided. Further, the video signal from the input terminal 11 is fed to the amplifier 1 via Tr1c to be introduced to the video signal output terminal 26. In this case, the values of the resistors 4, 6, 23, 24 are selected so that the collector current can be equal to Tr1c and 21c, and the sum of the collector current of Tr1a and 21a is made equal to the collector current of Tr21C. Thus, the current flowing to the resistor 5 is always kept constant. Accordingly, the output potential of the output terminal 26 is kept constant even if the DC potential fed to the terminal 12 to control the amplitude of the video output signal is changed.
COPYRIGHT: (C)1980,JPO&Japio
JP205579A 1979-01-10 1979-01-10 Processing circuit for television signal Granted JPS5593383A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP205579A JPS5593383A (en) 1979-01-10 1979-01-10 Processing circuit for television signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP205579A JPS5593383A (en) 1979-01-10 1979-01-10 Processing circuit for television signal

Publications (2)

Publication Number Publication Date
JPS5593383A true JPS5593383A (en) 1980-07-15
JPS6410155B2 JPS6410155B2 (en) 1989-02-21

Family

ID=11518642

Family Applications (1)

Application Number Title Priority Date Filing Date
JP205579A Granted JPS5593383A (en) 1979-01-10 1979-01-10 Processing circuit for television signal

Country Status (1)

Country Link
JP (1) JPS5593383A (en)

Also Published As

Publication number Publication date
JPS6410155B2 (en) 1989-02-21

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