JPS5591838A - Electronic device - Google Patents

Electronic device

Info

Publication number
JPS5591838A
JPS5591838A JP16397778A JP16397778A JPS5591838A JP S5591838 A JPS5591838 A JP S5591838A JP 16397778 A JP16397778 A JP 16397778A JP 16397778 A JP16397778 A JP 16397778A JP S5591838 A JPS5591838 A JP S5591838A
Authority
JP
Japan
Prior art keywords
resin
mold
electrode section
injection mold
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16397778A
Other languages
Japanese (ja)
Inventor
Fumio Takemoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP16397778A priority Critical patent/JPS5591838A/en
Publication of JPS5591838A publication Critical patent/JPS5591838A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE: To simplify the working of burying an electronic part into an dielectric, by burying the electronic part, such as a semiconductor element, etc., into the dielectric substrate, such as resin, etc., in such a position that the electrode section is selectively exposed, and also by providing its surface with an electric conductive wiring.
CONSTITUTION: A semiconductor chip 3 is set on the top of an injection mold's bottom mold 9, and a top mold 11 of the injection mold, which has a pin 10 contacting an electrode section 5 of the semiconductor chip, is set over the top. By injecting resin from a gate 12 provided on the bottom mold of the injection mold, a resin 8 is formed into a continuous piece around the semiconductor chip 3. As the electrode section 5 is exposed when the top and bottom molds are removed, a wiring 7 is provided in such a manner as to allow it to extend over the resin 8 by using photo etching process or printing process. The resin may be formed by using transfer mold, compression forming or injection mold. As this method eliminates necessity of photo-etching process to expose the electrode section, it is possible to shorten an entire fabricating process and improve quality.
COPYRIGHT: (C)1980,JPO&Japio
JP16397778A 1978-12-29 1978-12-29 Electronic device Pending JPS5591838A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16397778A JPS5591838A (en) 1978-12-29 1978-12-29 Electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16397778A JPS5591838A (en) 1978-12-29 1978-12-29 Electronic device

Publications (1)

Publication Number Publication Date
JPS5591838A true JPS5591838A (en) 1980-07-11

Family

ID=15784403

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16397778A Pending JPS5591838A (en) 1978-12-29 1978-12-29 Electronic device

Country Status (1)

Country Link
JP (1) JPS5591838A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6830954B2 (en) 2000-08-31 2004-12-14 Micron Technology, Inc. Transfer molding and underfilling method and apparatus

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6830954B2 (en) 2000-08-31 2004-12-14 Micron Technology, Inc. Transfer molding and underfilling method and apparatus
US6838319B1 (en) * 2000-08-31 2005-01-04 Micron Technology, Inc. Transfer molding and underfilling method and apparatus including orienting the active surface of a semiconductor substrate substantially vertically
US6863516B2 (en) 2000-08-31 2005-03-08 Micron Technology, Inc. Transfer molding and underfilling apparatus

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