JPS5550781A - Television image receiving device - Google Patents

Television image receiving device

Info

Publication number
JPS5550781A
JPS5550781A JP12384778A JP12384778A JPS5550781A JP S5550781 A JPS5550781 A JP S5550781A JP 12384778 A JP12384778 A JP 12384778A JP 12384778 A JP12384778 A JP 12384778A JP S5550781 A JPS5550781 A JP S5550781A
Authority
JP
Japan
Prior art keywords
circuit
sub
signal
main
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12384778A
Other languages
Japanese (ja)
Inventor
Yoshitaka Omori
Koji Ueda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP12384778A priority Critical patent/JPS5550781A/en
Publication of JPS5550781A publication Critical patent/JPS5550781A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To display irrespective of the synchronizing relation of the main CH and the sub CH by providing two sets of memory circuits in the TV image receiver receiving simultaneously the main channel CH and the sub CH.
CONSTITUTION: The radio wave from the antenna 1 is detected respectively by the detectors 6, 9 of the main CH and the sub CH, the respective horizontal and the vertical synchronous signals are separated in the synchronous separation circuits 7, 8 and transmitted to the control circuit 10. The output of the detecting circuit 9 of the sub CH is inputted to the memory circuit 13, the circuit 10 controls the circuit 13 by making the synchronous signal as reference and memorizes the signal from the circuit 9 successively. In the circuit 13, two pairs of the memory circuits, one of them reads while the other writes and the circuit 10 controls so as to do these operations alternately. During writing, the memory address is corresponded to the image signal of the sub CH, the signal of the sub CH is written correspondingly to the field in which the main CH is present and in the next field, the signal read from the first address and the signal of the main CH from the circuit 6 are alternately changed over in the mixing circuit 11 and displayed on CRT 15 through the image amplifier 14.
COPYRIGHT: (C)1980,JPO&Japio
JP12384778A 1978-10-05 1978-10-05 Television image receiving device Pending JPS5550781A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12384778A JPS5550781A (en) 1978-10-05 1978-10-05 Television image receiving device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12384778A JPS5550781A (en) 1978-10-05 1978-10-05 Television image receiving device

Publications (1)

Publication Number Publication Date
JPS5550781A true JPS5550781A (en) 1980-04-12

Family

ID=14870860

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12384778A Pending JPS5550781A (en) 1978-10-05 1978-10-05 Television image receiving device

Country Status (1)

Country Link
JP (1) JPS5550781A (en)

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