JPS5523613A - Reproducing system of timing information - Google Patents

Reproducing system of timing information

Info

Publication number
JPS5523613A
JPS5523613A JP9544878A JP9544878A JPS5523613A JP S5523613 A JPS5523613 A JP S5523613A JP 9544878 A JP9544878 A JP 9544878A JP 9544878 A JP9544878 A JP 9544878A JP S5523613 A JPS5523613 A JP S5523613A
Authority
JP
Japan
Prior art keywords
signal
timing information
ssx
circuit
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9544878A
Other languages
Japanese (ja)
Other versions
JPS6128B2 (en
Inventor
Kunihiro Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP9544878A priority Critical patent/JPS5523613A/en
Publication of JPS5523613A publication Critical patent/JPS5523613A/en
Publication of JPS6128B2 publication Critical patent/JPS6128B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To obtain the timing information with comparatively low cost, by using the output signal of the oscillator as the timing information for received digital signal sampling. CONSTITUTION:When the binary reception data signal SSX is incoming, it is inputted to the delay circyit DL. FFD1 is triggered with the leading edge of the output clock signal SVCO of the oscillator VCO to set the input side signal SSX of the circuit DL. FFD2 is similarly triggered to set the output signal SDL of the circuit DL. Similarly, FFD3,D4 set the input and output signals SSX and SDL of the circuit DL. The exclusive OR gate E1 inputs the output signals SD1,SD2 of FFD1 and FFD2. Further, the exclusive OR gate E2 inputs the output signals SD3,SD4 of FFD3 and FFD4. Further, when the logic 1 signal is inputted to the FAST,SLOW terminals of the oscillator VCO, the oscillated frequency is increased to retard the phase through the lead or lag phase of oscillation.
JP9544878A 1978-08-07 1978-08-07 Reproducing system of timing information Granted JPS5523613A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9544878A JPS5523613A (en) 1978-08-07 1978-08-07 Reproducing system of timing information

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9544878A JPS5523613A (en) 1978-08-07 1978-08-07 Reproducing system of timing information

Publications (2)

Publication Number Publication Date
JPS5523613A true JPS5523613A (en) 1980-02-20
JPS6128B2 JPS6128B2 (en) 1986-01-06

Family

ID=14137966

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9544878A Granted JPS5523613A (en) 1978-08-07 1978-08-07 Reproducing system of timing information

Country Status (1)

Country Link
JP (1) JPS5523613A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01293039A (en) * 1988-05-20 1989-11-27 Nitsuko Corp Synchronizing system
EP0490273A2 (en) * 1990-12-10 1992-06-17 Advantest Corporation Retiming circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01293039A (en) * 1988-05-20 1989-11-27 Nitsuko Corp Synchronizing system
EP0490273A2 (en) * 1990-12-10 1992-06-17 Advantest Corporation Retiming circuit
EP0490273A3 (en) * 1990-12-10 1992-12-09 Advantest Corporation Retiming circuit

Also Published As

Publication number Publication date
JPS6128B2 (en) 1986-01-06

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