JPS54148413A - Reproduction system for timing information - Google Patents

Reproduction system for timing information

Info

Publication number
JPS54148413A
JPS54148413A JP5667478A JP5667478A JPS54148413A JP S54148413 A JPS54148413 A JP S54148413A JP 5667478 A JP5667478 A JP 5667478A JP 5667478 A JP5667478 A JP 5667478A JP S54148413 A JPS54148413 A JP S54148413A
Authority
JP
Japan
Prior art keywords
vco
ssx
gate
supplied
sampling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5667478A
Other languages
Japanese (ja)
Other versions
JPS6117382B2 (en
Inventor
Kunihiro Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP5667478A priority Critical patent/JPS54148413A/en
Publication of JPS54148413A publication Critical patent/JPS54148413A/en
Publication of JPS6117382B2 publication Critical patent/JPS6117382B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To obtain the timing signal for sampling in a comparatively economical way for the digital receiver by sampling the reception signal with the rise of the VCO clock. CONSTITUTION:Reception signal SSX is sampled D1 with the rise of the VCO clock and then supplied to exclusive OR gate E along with the signal delayed D2 by the SSX interval time. When the comparison result has no agreement, logic 1 is delivered from E and then supplied to VCO via AND gate A1 and A2 to control the phase of VCO. The output of VCO undergoes 2-division D3 to be used as the sampling clock as well as to be supplied to gate A1 and A2. Thus, SSX is sampled by the rise edge of the output signal of D3 to minimize the error.
JP5667478A 1978-05-15 1978-05-15 Reproduction system for timing information Granted JPS54148413A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5667478A JPS54148413A (en) 1978-05-15 1978-05-15 Reproduction system for timing information

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5667478A JPS54148413A (en) 1978-05-15 1978-05-15 Reproduction system for timing information

Publications (2)

Publication Number Publication Date
JPS54148413A true JPS54148413A (en) 1979-11-20
JPS6117382B2 JPS6117382B2 (en) 1986-05-07

Family

ID=13033957

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5667478A Granted JPS54148413A (en) 1978-05-15 1978-05-15 Reproduction system for timing information

Country Status (1)

Country Link
JP (1) JPS54148413A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61273038A (en) * 1985-05-28 1986-12-03 Nec Corp Clock synchronous circuit

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0140788Y2 (en) * 1985-05-24 1989-12-05
JPS6437782U (en) * 1987-09-01 1989-03-07

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4960813A (en) * 1972-10-17 1974-06-13
JPS4960863A (en) * 1972-10-17 1974-06-13
JPS4967551A (en) * 1972-10-17 1974-07-01

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4960813A (en) * 1972-10-17 1974-06-13
JPS4960863A (en) * 1972-10-17 1974-06-13
JPS4967551A (en) * 1972-10-17 1974-07-01

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61273038A (en) * 1985-05-28 1986-12-03 Nec Corp Clock synchronous circuit

Also Published As

Publication number Publication date
JPS6117382B2 (en) 1986-05-07

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