JPS55117387A - Connection switch control system for inter-frame coding device - Google Patents

Connection switch control system for inter-frame coding device

Info

Publication number
JPS55117387A
JPS55117387A JP2498879A JP2498879A JPS55117387A JP S55117387 A JPS55117387 A JP S55117387A JP 2498879 A JP2498879 A JP 2498879A JP 2498879 A JP2498879 A JP 2498879A JP S55117387 A JPS55117387 A JP S55117387A
Authority
JP
Japan
Prior art keywords
frame
inter
signal
decoding
frame coding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2498879A
Other languages
Japanese (ja)
Inventor
Makoto Hiraoka
Hiroshi Yasuda
Yoshiichiro Inamura
Shuzo Tsukane
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, NEC Corp, Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical Fujitsu Ltd
Priority to JP2498879A priority Critical patent/JPS55117387A/en
Publication of JPS55117387A publication Critical patent/JPS55117387A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
    • H04N19/503—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving temporal prediction

Abstract

PURPOSE:To prevent the lowering of the picture quality at the connection switching time of the inter-frame coding device by opening both the inter-frame coding loop of the transmitter side and the inter-frame decoding loop of the receiver side for 1- frame time. CONSTITUTION:Control circuits CONTS and CONTR switch switching circits SWS and SWR toward constant level CLV via switch command signal SS. Singal CLV is selected to the value near the central level of the input signal where the input of coder COD within the frame becomes minimum. As a result, only the signal that is coded within the frame is transmitted, and the decoding is carried out only by decoder DEC within the frame. Accordingly, the coincidence is secured for the contents between 1-frame memories FMS and FMR. Thus circuit CONTS switches circuit SWS toward memory FMS after 1-frame time to carry out the inter-frame coding. At the same time, special code signal CD is applied to multiplexer MPX. The receiver side starts the inter-frame decoding after detection of signal CD.
JP2498879A 1979-03-02 1979-03-02 Connection switch control system for inter-frame coding device Pending JPS55117387A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2498879A JPS55117387A (en) 1979-03-02 1979-03-02 Connection switch control system for inter-frame coding device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2498879A JPS55117387A (en) 1979-03-02 1979-03-02 Connection switch control system for inter-frame coding device

Publications (1)

Publication Number Publication Date
JPS55117387A true JPS55117387A (en) 1980-09-09

Family

ID=12153354

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2498879A Pending JPS55117387A (en) 1979-03-02 1979-03-02 Connection switch control system for inter-frame coding device

Country Status (1)

Country Link
JP (1) JPS55117387A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61114675A (en) * 1984-11-08 1986-06-02 Nippon Telegr & Teleph Corp <Ntt> Refreshing system in coding between frames
WO1989003159A2 (en) * 1987-10-05 1989-04-06 Intel Corporation Digital video compression system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61114675A (en) * 1984-11-08 1986-06-02 Nippon Telegr & Teleph Corp <Ntt> Refreshing system in coding between frames
WO1989003159A2 (en) * 1987-10-05 1989-04-06 Intel Corporation Digital video compression system

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