JPS5485619A - Digital transmission device - Google Patents
Digital transmission deviceInfo
- Publication number
- JPS5485619A JPS5485619A JP15392077A JP15392077A JPS5485619A JP S5485619 A JPS5485619 A JP S5485619A JP 15392077 A JP15392077 A JP 15392077A JP 15392077 A JP15392077 A JP 15392077A JP S5485619 A JPS5485619 A JP S5485619A
- Authority
- JP
- Japan
- Prior art keywords
- information
- buffer memory
- unit
- amount
- memory unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
- H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
- H04N21/236—Assembling of a multiplex stream, e.g. transport stream, by combining a video stream with other content or additional data, e.g. inserting a URL [Uniform Resource Locator] into a video stream, multiplexing software data into a video stream; Remultiplexing of multiplex streams; Insertion of stuffing bits into the multiplex stream, e.g. to obtain a constant bit-rate; Assembling of a packetised elementary stream
- H04N21/2365—Multiplexing of several video streams
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L5/00—Arrangements affording multiple use of the transmission path
- H04L5/22—Arrangements affording multiple use of the transmission path using time-division multiplexing
- H04L5/24—Arrangements affording multiple use of the transmission path using time-division multiplexing with start-stop synchronous converters
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/434—Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream
- H04N21/4347—Demultiplexing of several video streams
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Multimedia (AREA)
- Computer Networks & Wireless Communication (AREA)
- Dc Digital Transmission (AREA)
- Communication Control (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Time-Division Multiplex Systems (AREA)
Abstract
PURPOSE:To set the capacity of the reception buffer memory unit to the minimum necessary amount by setting the propagation delay time to the prescribed value for the information from the input of the transmission buffer memory unit to the output of the reception buffer memory unit. CONSTITUTION:At the transmission terminal, the transmitting information amount which is read out from transmission buffer memory unit 112 and then transmitted in a fixed time is counted through transmitting information amount counter circuit 115, and the transmitting information amount and the information storage amount of unit 112 are transmitted in the form of the control information through control information multiplying circuit 113. While at the reception terminal, the control information is isolated 121 from the receiving information, and the output and the reading time of the information given from reception buffer memory 122 are controlled 123 in order to secure the constant setting to a fixed time for the propagation delay time of the information from the input of unit 112 to the output of 122. Thus, the memory capacity of unit 122 can be set to the minimum necessary amount.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15392077A JPS5485619A (en) | 1977-12-20 | 1977-12-20 | Digital transmission device |
US05/970,051 US4215369A (en) | 1977-12-20 | 1978-12-15 | Digital transmission system for television video signals |
CA318,184A CA1132243A (en) | 1977-12-20 | 1978-12-19 | Digital transmission system for television video signals |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15392077A JPS5485619A (en) | 1977-12-20 | 1977-12-20 | Digital transmission device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5485619A true JPS5485619A (en) | 1979-07-07 |
JPS63977B2 JPS63977B2 (en) | 1988-01-09 |
Family
ID=15572974
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15392077A Granted JPS5485619A (en) | 1977-12-20 | 1977-12-20 | Digital transmission device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5485619A (en) |
-
1977
- 1977-12-20 JP JP15392077A patent/JPS5485619A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS63977B2 (en) | 1988-01-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS5327332A (en) | Sound response unit of entirely double type | |
JPS5392613A (en) | Data transmission system | |
JPS5485619A (en) | Digital transmission device | |
JPS5768949A (en) | Buffer memory control system in packet transmission | |
JPS5442961A (en) | Receiver | |
JPS5415620A (en) | Buffer memory unit | |
JPS52110531A (en) | Memory unit | |
JPS56748A (en) | Phase control circuit | |
JPS5438732A (en) | Input/output order accepting system | |
JPS54128215A (en) | Buffer memory unit | |
JPS5733472A (en) | Memory access control system | |
JPS53113437A (en) | Semiconductor memory unit | |
JPS56106451A (en) | Multiplication/isolation circuit | |
JPS5411648A (en) | Semiconductor memory unit | |
JPS5718069A (en) | Information storage device | |
SU653751A1 (en) | Apparatus for remote checking of linear regenerators | |
JPS56168251A (en) | Data transfer buffer system | |
JPS5781760A (en) | Highway test device | |
JPS57191750A (en) | Buffer memory device | |
JPS5440006A (en) | Buffer control unit | |
JPS57119543A (en) | Control station device | |
JPS56105549A (en) | Memory controlling unit | |
JPS5329480A (en) | Program controller | |
JPS57189256A (en) | Digital signal processor | |
JPS5620362A (en) | Error information system |