JPS5462735A - Memory control system - Google Patents
Memory control systemInfo
- Publication number
- JPS5462735A JPS5462735A JP12926977A JP12926977A JPS5462735A JP S5462735 A JPS5462735 A JP S5462735A JP 12926977 A JP12926977 A JP 12926977A JP 12926977 A JP12926977 A JP 12926977A JP S5462735 A JPS5462735 A JP S5462735A
- Authority
- JP
- Japan
- Prior art keywords
- address
- error
- register
- eas
- information
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
- Debugging And Monitoring (AREA)
Abstract
PURPOSE: To speed up an interruption process with the overhead of software reduced, by building a microprocessor in an arithmetic control unit and by computing an error address through the software.
CONSTITUTION: In arithmetic control unit ACU1, error address register 11, branch register BR, and buffer register BF are built in addition to the microprocessor. Pieces of error check information PO to Pn in register 11 are stored in BR, and error address head address EAS is in BF. On the basis of information in BR, whether access to the main memory is attained in UP or DOWN direction and how many addresses away from EAS the error-occurrence address is are both discriminated, and on the basis of the discrimination information, the error address is corrected, thereby writing the error actual address in the error address storage address.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12926977A JPS5462735A (en) | 1977-10-28 | 1977-10-28 | Memory control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12926977A JPS5462735A (en) | 1977-10-28 | 1977-10-28 | Memory control system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5462735A true JPS5462735A (en) | 1979-05-21 |
Family
ID=15005395
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12926977A Pending JPS5462735A (en) | 1977-10-28 | 1977-10-28 | Memory control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5462735A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2006100776A1 (en) * | 2005-03-24 | 2006-09-28 | Fujitsu Limited | Memory address management by firmware |
KR100922409B1 (en) | 2005-03-24 | 2009-10-16 | 후지쯔 가부시끼가이샤 | Information processing device and memory anomaly monitoring method |
-
1977
- 1977-10-28 JP JP12926977A patent/JPS5462735A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2006100776A1 (en) * | 2005-03-24 | 2006-09-28 | Fujitsu Limited | Memory address management by firmware |
JPWO2006100776A1 (en) * | 2005-03-24 | 2008-08-28 | 富士通株式会社 | Memory error address management by firmware |
KR100922409B1 (en) | 2005-03-24 | 2009-10-16 | 후지쯔 가부시끼가이샤 | Information processing device and memory anomaly monitoring method |
JP4523639B2 (en) * | 2005-03-24 | 2010-08-11 | 富士通株式会社 | Memory error address management by firmware |
US8527806B2 (en) | 2005-03-24 | 2013-09-03 | Fujitsu Limited | Information processing device and memory anomaly monitoring method |
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