JPS5464944A - Buffer invalidating system for multi-cpu system - Google Patents

Buffer invalidating system for multi-cpu system

Info

Publication number
JPS5464944A
JPS5464944A JP13073677A JP13073677A JPS5464944A JP S5464944 A JPS5464944 A JP S5464944A JP 13073677 A JP13073677 A JP 13073677A JP 13073677 A JP13073677 A JP 13073677A JP S5464944 A JPS5464944 A JP S5464944A
Authority
JP
Japan
Prior art keywords
cpu
intra
office
invalidating
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13073677A
Other languages
Japanese (ja)
Other versions
JPS6012670B2 (en
Inventor
Takashi Sakai
Hiroshi Hayashi
Masatake Iwato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP52130736A priority Critical patent/JPS6012670B2/en
Publication of JPS5464944A publication Critical patent/JPS5464944A/en
Publication of JPS6012670B2 publication Critical patent/JPS6012670B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Multi Processors (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To simplify the multi-CPU system by providing each CPU the function to inform the invalidating state to other CPU and furthermore distributing the address lines to be the invalidating object between CPU's.
CONSTITUTION: Common bus 12 which combines between CPU11-OW11-3 and each of these CPU's is provided, along with main storage unit 13 which is used in common by CPU11-0W11-3 connected together via bus 12. Thus, part or whole of buffer storages 14-0W14-3 which are incorporated into the above CPU's is invalidated. By the flag detection gates 15-0W15-3 provided to these CPU's, whether the flag byte showing the storage command is on bus 12 is detected. In case the flag byte exists, the address to be stored in unit 13 is memorized in intra-office address registers 16-0W16-3. And then whether the addresses corresponding to intra-office registers 14-0W14-3 exist or not is collated. When a coincidence is obtained in the above collation, the intra-office storage is invalidated.
COPYRIGHT: (C)1979,JPO&Japio
JP52130736A 1977-11-02 1977-11-02 Buffer invalidation method in multi-CPU system Expired JPS6012670B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52130736A JPS6012670B2 (en) 1977-11-02 1977-11-02 Buffer invalidation method in multi-CPU system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52130736A JPS6012670B2 (en) 1977-11-02 1977-11-02 Buffer invalidation method in multi-CPU system

Publications (2)

Publication Number Publication Date
JPS5464944A true JPS5464944A (en) 1979-05-25
JPS6012670B2 JPS6012670B2 (en) 1985-04-02

Family

ID=15041389

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52130736A Expired JPS6012670B2 (en) 1977-11-02 1977-11-02 Buffer invalidation method in multi-CPU system

Country Status (1)

Country Link
JP (1) JPS6012670B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5647982A (en) * 1979-09-28 1981-04-30 Hitachi Ltd Cash memory control system
JPS57172582A (en) * 1981-04-15 1982-10-23 Hitachi Ltd Cash memory control method
JPS5864690A (en) * 1981-10-14 1983-04-18 Hitachi Ltd Control method for cash memory
JPS6232553A (en) * 1985-08-06 1987-02-12 Nec Corp Cache memory system
JPS62288949A (en) * 1986-06-09 1987-12-15 Fujitsu Ltd Serializing instruction control system

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5647982A (en) * 1979-09-28 1981-04-30 Hitachi Ltd Cash memory control system
JPS57172582A (en) * 1981-04-15 1982-10-23 Hitachi Ltd Cash memory control method
JPH0127455B2 (en) * 1981-04-15 1989-05-29 Hitachi Seisakusho Kk
JPS5864690A (en) * 1981-10-14 1983-04-18 Hitachi Ltd Control method for cash memory
JPS6232553A (en) * 1985-08-06 1987-02-12 Nec Corp Cache memory system
JPS62288949A (en) * 1986-06-09 1987-12-15 Fujitsu Ltd Serializing instruction control system
JPH06103476B2 (en) * 1986-06-09 1994-12-14 富士通株式会社 Serialize instruction controller

Also Published As

Publication number Publication date
JPS6012670B2 (en) 1985-04-02

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