JPS5449040A - Check unit for logic circuit - Google Patents

Check unit for logic circuit

Info

Publication number
JPS5449040A
JPS5449040A JP11583877A JP11583877A JPS5449040A JP S5449040 A JPS5449040 A JP S5449040A JP 11583877 A JP11583877 A JP 11583877A JP 11583877 A JP11583877 A JP 11583877A JP S5449040 A JPS5449040 A JP S5449040A
Authority
JP
Japan
Prior art keywords
circuit
signal
logic circuit
difference
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11583877A
Other languages
Japanese (ja)
Inventor
Teruhiko Yamada
Yoshihiro Kasuya
Mikiyuki Zaisho
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11583877A priority Critical patent/JPS5449040A/en
Publication of JPS5449040A publication Critical patent/JPS5449040A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To check a logic circuit strictly, by detecting not only the difference in output signal in a steady state between a checked logic circuit and reference logic circuit but also the difference in output signal in a transient state.
CONSTITUTION: The delay time of data set signal generating circuit 1 is set to the time when quality decision circuits 5 and 7 are reset by clock pulse C. Then, the delay time of sampling signal generating circuit 6 is set to a time much longer than that check input signal group 1 is set to data register 2 synchronizing with data set signal C1 and checked logic circuit 3 and reference logic circuit 4 answer to output signal 1' of circuit 2 and are steady. Next, circuit 5 detects the difference between signal groups X1 and X2 of circuits 3 and 4 at a time preset by signal C, and circuit 7 detected an undesired pulse signal generated transiently in the output of circuit 3
COPYRIGHT: (C)1979,JPO&Japio
JP11583877A 1977-09-26 1977-09-26 Check unit for logic circuit Pending JPS5449040A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11583877A JPS5449040A (en) 1977-09-26 1977-09-26 Check unit for logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11583877A JPS5449040A (en) 1977-09-26 1977-09-26 Check unit for logic circuit

Publications (1)

Publication Number Publication Date
JPS5449040A true JPS5449040A (en) 1979-04-18

Family

ID=14672361

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11583877A Pending JPS5449040A (en) 1977-09-26 1977-09-26 Check unit for logic circuit

Country Status (1)

Country Link
JP (1) JPS5449040A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5933561A (en) * 1982-08-20 1984-02-23 Fujitsu Ltd Diagnostic system of computer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5933561A (en) * 1982-08-20 1984-02-23 Fujitsu Ltd Diagnostic system of computer
JPH0410100B2 (en) * 1982-08-20 1992-02-24

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