JPS54154225A - Display unit - Google Patents

Display unit

Info

Publication number
JPS54154225A
JPS54154225A JP6220778A JP6220778A JPS54154225A JP S54154225 A JPS54154225 A JP S54154225A JP 6220778 A JP6220778 A JP 6220778A JP 6220778 A JP6220778 A JP 6220778A JP S54154225 A JPS54154225 A JP S54154225A
Authority
JP
Japan
Prior art keywords
memory
pattern
graphic
displayed
memorizes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6220778A
Other languages
Japanese (ja)
Other versions
JPS5912177B2 (en
Inventor
Tsuguo Sakamoto
Kenji Masai
Yoshi Ozaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Engineering Co Ltd
Hitachi Ltd
Original Assignee
Hitachi Engineering Co Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Engineering Co Ltd, Hitachi Ltd filed Critical Hitachi Engineering Co Ltd
Priority to JP6220778A priority Critical patent/JPS5912177B2/en
Publication of JPS54154225A publication Critical patent/JPS54154225A/en
Publication of JPS5912177B2 publication Critical patent/JPS5912177B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To secure the highly effective application of the graphic memory by displaying the memory pattern of the graphic memory with the vertical and horizontal inversion at the actual displaying time.
CONSTITUTION: Refresh memory 10 memorizes the screen data to be displayed, and graphic memory 20 memorizes the graphic data to be displayed respectively. And the raster synchronous signal is delivered through timing circuit 40, and the pattern data corresponding to each screen data are delivered from pattern generating circuit 30. The memory pattern of memory 20 is displayed 6 with vertical and horizontal inversion at the actual displaying time. In such way, a highly effective application is ensured for memory 20.
COPYRIGHT: (C)1979,JPO&Japio
JP6220778A 1978-05-26 1978-05-26 display device Expired JPS5912177B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6220778A JPS5912177B2 (en) 1978-05-26 1978-05-26 display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6220778A JPS5912177B2 (en) 1978-05-26 1978-05-26 display device

Publications (2)

Publication Number Publication Date
JPS54154225A true JPS54154225A (en) 1979-12-05
JPS5912177B2 JPS5912177B2 (en) 1984-03-21

Family

ID=13193457

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6220778A Expired JPS5912177B2 (en) 1978-05-26 1978-05-26 display device

Country Status (1)

Country Link
JP (1) JPS5912177B2 (en)

Also Published As

Publication number Publication date
JPS5912177B2 (en) 1984-03-21

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