JPS54137244A - Graphic display unit - Google Patents

Graphic display unit

Info

Publication number
JPS54137244A
JPS54137244A JP4568278A JP4568278A JPS54137244A JP S54137244 A JPS54137244 A JP S54137244A JP 4568278 A JP4568278 A JP 4568278A JP 4568278 A JP4568278 A JP 4568278A JP S54137244 A JPS54137244 A JP S54137244A
Authority
JP
Japan
Prior art keywords
memory
address
contents
generator
picture element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4568278A
Other languages
Japanese (ja)
Inventor
Yoshio Yui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP4568278A priority Critical patent/JPS54137244A/en
Publication of JPS54137244A publication Critical patent/JPS54137244A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To secure the instantaneous change for part or whole of the screen of the display contents with no alteration of the memory contents by providing the converter to change the conversion contents between the data read out from the memory groups and the video signals.
CONSTITUTION: Address generator 1 separates the display screen into the picture element unit and one group of plural picture element units in accordance with the sequential scanning. In addition to generator 1, plural memory groups 3 are provided to form the part corresponding to the picture element unit as the bit more than 2 with reception of address 2 corresponding to the vivided display screens. Then paired memory 10 is added to memorize the signals sent from address control input 9, along with address arithmetic unit 11 to compare the output of memory 10 with address 2 of generator 1. Thus, whether or not the tetragon on the screen is scanned is decided. At the same time, the conversion data given from data register control input 13 is given to comparator 7 together with the output of converter 11 and each output of memory group 3 via buffer 5, thus part or whole of the display contents being changed instantaneously.
COPYRIGHT: (C)1979,JPO&Japio
JP4568278A 1978-04-17 1978-04-17 Graphic display unit Pending JPS54137244A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4568278A JPS54137244A (en) 1978-04-17 1978-04-17 Graphic display unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4568278A JPS54137244A (en) 1978-04-17 1978-04-17 Graphic display unit

Publications (1)

Publication Number Publication Date
JPS54137244A true JPS54137244A (en) 1979-10-24

Family

ID=12726155

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4568278A Pending JPS54137244A (en) 1978-04-17 1978-04-17 Graphic display unit

Country Status (1)

Country Link
JP (1) JPS54137244A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007333244A (en) * 2006-06-12 2007-12-27 Sanyo Electric Co Ltd Storage

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007333244A (en) * 2006-06-12 2007-12-27 Sanyo Electric Co Ltd Storage

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