JPS54139338A - Character display device - Google Patents

Character display device

Info

Publication number
JPS54139338A
JPS54139338A JP4755178A JP4755178A JPS54139338A JP S54139338 A JPS54139338 A JP S54139338A JP 4755178 A JP4755178 A JP 4755178A JP 4755178 A JP4755178 A JP 4755178A JP S54139338 A JPS54139338 A JP S54139338A
Authority
JP
Japan
Prior art keywords
circuit
address
character
cpu
rom
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4755178A
Other languages
Japanese (ja)
Other versions
JPS6115431B2 (en
Inventor
Tsuguji Tateuchi
Shigeru Hirahata
Teruhiro Takezawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP4755178A priority Critical patent/JPS54139338A/en
Publication of JPS54139338A publication Critical patent/JPS54139338A/en
Publication of JPS6115431B2 publication Critical patent/JPS6115431B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To obtain a character display circuit which uses a ROM efficiently and economically, by storing program information and character pattern information in the one-system ROM and providing a switch circuit in each of ROM address input and data output.
CONSTITUTION: Assuming that address switch circuit 7, address signal switch circuit 26 and information signal switch circuit 28 are switched to the address bus 5 of CPU 1, the bus 5 side of CPU 1 and the data bus 4 side respectively, character code signals are stored in system character pattern common ROM 27 together with program information. The address of the picture displayed by CPU 1 and character code signals are inputted to character display driving circuit 15 and are stored into character storing RAM 8 in circuit 15. CPU 1 uses control signals to switch circuits 26 and 28 to the RAM 8 side and the parallel-series converter circuit 10 side respectively, and video signals of character display which were subjected to parallel-series conversion are obtained from circuit 10 by address signals from timing pulse generator circuit 6.
COPYRIGHT: (C)1979,JPO&Japio
JP4755178A 1978-04-20 1978-04-20 Character display device Granted JPS54139338A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4755178A JPS54139338A (en) 1978-04-20 1978-04-20 Character display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4755178A JPS54139338A (en) 1978-04-20 1978-04-20 Character display device

Publications (2)

Publication Number Publication Date
JPS54139338A true JPS54139338A (en) 1979-10-29
JPS6115431B2 JPS6115431B2 (en) 1986-04-24

Family

ID=12778288

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4755178A Granted JPS54139338A (en) 1978-04-20 1978-04-20 Character display device

Country Status (1)

Country Link
JP (1) JPS54139338A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56154788A (en) * 1980-04-30 1981-11-30 Sharp Kk Display signal decoding system
JPS62240995A (en) * 1986-04-14 1987-10-21 株式会社東芝 Memory

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3760375A (en) * 1954-05-20 1973-09-18 Sycor Inc Source data entry terminal

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3760375A (en) * 1954-05-20 1973-09-18 Sycor Inc Source data entry terminal

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56154788A (en) * 1980-04-30 1981-11-30 Sharp Kk Display signal decoding system
JPS62240995A (en) * 1986-04-14 1987-10-21 株式会社東芝 Memory

Also Published As

Publication number Publication date
JPS6115431B2 (en) 1986-04-24

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