JPS54124612A - Receiving data detector circuit in data transmission - Google Patents

Receiving data detector circuit in data transmission

Info

Publication number
JPS54124612A
JPS54124612A JP3249078A JP3249078A JPS54124612A JP S54124612 A JPS54124612 A JP S54124612A JP 3249078 A JP3249078 A JP 3249078A JP 3249078 A JP3249078 A JP 3249078A JP S54124612 A JPS54124612 A JP S54124612A
Authority
JP
Japan
Prior art keywords
receiving data
output
polarity
flop
flip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3249078A
Other languages
Japanese (ja)
Inventor
Hiroyuki Matsumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP3249078A priority Critical patent/JPS54124612A/en
Publication of JPS54124612A publication Critical patent/JPS54124612A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

PURPOSE:To make it possible to use a good-transmission efficiency continuous synchronous system by detecting the polarity of receiving data and generating clocks which performs correctly sampling of receiving data on a basis of this detected polarity. CONSTITUTION:When the polarity of receiving data input 1 is changed, counter 10 is cleared forcedly, and output 13 becomes ''1'' for the purpose of setting forcedly flip-flop 12 which generates clocks for performing correctly sampling of receiving data. After that, output 13 of flip-flop 12 is changed from ''1'' to ''0'' at the logical center of receiving bits. Further, if receiving data bits have the same polarity, output 13 is changed from ''0'' to ''1'' at the boundary point of logical data bits. As a result, when receiving data input 1 is subjected to sampling at the trailing edge of output 13 of flip-flop 12, receiving data can be received correctly.
JP3249078A 1978-03-22 1978-03-22 Receiving data detector circuit in data transmission Pending JPS54124612A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3249078A JPS54124612A (en) 1978-03-22 1978-03-22 Receiving data detector circuit in data transmission

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3249078A JPS54124612A (en) 1978-03-22 1978-03-22 Receiving data detector circuit in data transmission

Publications (1)

Publication Number Publication Date
JPS54124612A true JPS54124612A (en) 1979-09-27

Family

ID=12360424

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3249078A Pending JPS54124612A (en) 1978-03-22 1978-03-22 Receiving data detector circuit in data transmission

Country Status (1)

Country Link
JP (1) JPS54124612A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0054322A1 (en) * 1980-12-12 1982-06-23 Philips Electronics Uk Limited Phase sensitive detector
FR2498032A1 (en) * 1981-01-12 1982-07-16 Sangamo Weston BIT SYNCHRONIZER FOR DIGITAL SIGNALS

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5185660A (en) * 1975-01-24 1976-07-27 Tokyo Shibaura Electric Co

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5185660A (en) * 1975-01-24 1976-07-27 Tokyo Shibaura Electric Co

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0054322A1 (en) * 1980-12-12 1982-06-23 Philips Electronics Uk Limited Phase sensitive detector
FR2498032A1 (en) * 1981-01-12 1982-07-16 Sangamo Weston BIT SYNCHRONIZER FOR DIGITAL SIGNALS

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